Cyclone V PCIE Hard IP

I'm presently checking if CvP might be enabled in a Cyclone V GX PCIe design of 2012 by pure code redesign, of if hardware changes could be necessary.

--- Quote Start ---

For Cyclone V device, you need to use the nPERSTL1 for the reset controller.

--- Quote End ---

That's in fact written in the CvP user guide. But the Cyclone V specific PCIe user guide tells:

--- Quote Start ---

• NPERSTL0: bottom left Hard IP and CvP blocks

• NPERSTL1: top left Hard IP block

• NPERSTR0: bottom right Hard IP block

• NPERSTR1: top right Hard IP block

For example, if you are using the Hard IP instance in the bottom

left corner of the device, you must connect pin_perst to

NPERSL0.

For maximum use of the Cyclone V device, Altera recommends

that you use the bottom left Hard IP first. This is the only

location that supports CvP over a PCIe link. If your design does

not require CvP, you may select other Hard IP blocks.

--- Quote End ---

This sounds more reasonable because NPERSTL0 is assigned to the bottom left PCIe hard IP incorporating the CVP function. It's also the configuration provided by the Altera Cyclone V GX FPGA Dev Kit. Unless someone can give a good explanation for the statement in the CvP user guide, I presume it's a typo.

To ask a subsequent question, did somebody already implement CvP with Cyclone V GX and can comment about correctness of the documentation.

Another simple question, I have been using Quartus 13.1 up to now, it tells me "CvP not supported for Cyclone V" when I try to enable it in the device configuration. Is it so that Cyclone V CvP requires Quartus 14 or did I anything (not obviously) wrong?

Regards,

Frank