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Altera_Forum
Honored Contributor
Honored ContributorCyclone V PCIE Hard IP
We want use pcie Configuration via Protocol, but we are confused with the pcie reset controller. which pin can be used for pcie_npor_npor and pcie_npor_pin_perst? if use the CvP function, is...
Altera_ForumHonored Contributor
Honored ContributorThe info in CvP user guide "...use the nPERSTL1 for the reset controller." is correct.
The info in Cyclone V PCIe user guide ' NPERSTL0: bottom left Hard IP and CvP blocks" is a typo. The correction is " ' NPERSTL1: bottom left Hard IP and CvP blocks"" Please note that the NPERST mapping for Cyclone V is opposite for Stratix V and Arria V (where bottom HIP is associated with nPERSTL0, top HIP is associated with nPERSTL1). The correct mapping for Cyclone V is: TOP PCIe HIP --> nPERSTL0 BOTTOM PCIe HIP --> nPERSTL1
