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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V LVDS_Rx input clk

hi,

I am working with Cyclone V to receive high rate data from ADC,the clock from ADC is 500MHz, but the LVDS_rx input clock(f hsclkin on datasheet）can only be 437.5MHz.and then, When i generate LVDS_rx IP, the input clk can be configured to 500MHz.

i want to know which is right? Can this device meet my requirements？

Thanks

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    In this case, you have to refer to the datasheet "High-Speed I/O Specifications" for your Cyclone V speed grade. Maximum input data rate with -C6 is 840 MHz, respectively 420 MHz clock.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    In this case, you have to refer to the datasheet "High-Speed I/O Specifications" for your Cyclone V speed grade. Maximum input data rate with -C6 is 840 MHz, respectively 420 MHz clock.

    --- Quote End ---

    Thanks for your reply.

    does this means that Cyclone V only can receive data in DDR mode to reach high data bandwidth as 840MHz?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes. Which data rate do you try to achieve 1000 MHz DDR or 500 MHz SDR?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Yes. Which data rate do you try to achieve 1000 MHz DDR or 500 MHz SDR?

    --- Quote End ---

    Thanks.

    I need to receive data 500Mbps, so now the clock coming into Cyclone V must be 250MHz.

    In addition, can cyclone V receive these data correctly without DPA?

    Looking forward your advice.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    can cyclone V receive these data correctly without DPA?

    --- Quote End ---

    Probably yes. What's the ADC type?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Probably yes. What's the ADC type?

    --- Quote End ---

    I am planning to use ADC08D1020 and to receive 32bit data lines use an lvds_rx megafuction with the following parameters:

    input clock:250MHz;

    data rate:500Mbps;

    The Cyclone V devices don't have DPA.

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    500 MHz data rate should allow sufficient sample window to operate the receiver with fixed phase relative to DCLK.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hello I am doing a similar design but with four ADCs and in a Cyclone 3.

    However I am confused about the LVDS clock signal input: are all the input clock IO pins dedicated LVDS? I do not want to have problems about clock mismatches so I need to confirm the IO input clock pin is LVDS compatible, no emulated? I know that for transmitters the question is different but for receivers I didn't find any information.

    Thanks in advance.

    Regards