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Altera_Forum
Honored Contributor
Honored ContributorCyclone V LVDS_Rx input clk
hi, I am working with Cyclone V to receive high rate data from ADC,the clock from ADC is 500MHz, but the LVDS_rx input clock(f hsclkin on datasheet）can only be 437.5MHz.and then, When i ...
Altera_ForumHonored Contributor
Honored Contributor500 MHz data rate should allow sufficient sample window to operate the receiver with fixed phase relative to DCLK.
