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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone V LVDS_Rx input clk

hi, I am working with Cyclone V to receive high rate data from ADC,the clock from ADC is 500MHz, but the LVDS_rx input clock(f hsclkin on datasheet）can only be 437.5MHz.and then, When i ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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In this case, you have to refer to the datasheet "High-Speed I/O Specifications" for your Cyclone V speed grade. Maximum input data rate with -C6 is 840 MHz, respectively 420 MHz clock.

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Thanks for your reply.

does this means that Cyclone V only can receive data in DDR mode to reach high data bandwidth as 840MHz?