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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone V LVDS_Rx input clk

hi, I am working with Cyclone V to receive high rate data from ADC,the clock from ADC is 500MHz, but the LVDS_rx input clock(f hsclkin on datasheet）can only be 437.5MHz.and then, When i ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Probably yes. What's the ADC type?

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I am planning to use ADC08D1020 and to receive 32bit data lines use an lvds_rx megafuction with the following parameters:

input clock:250MHz;

data rate:500Mbps;

The Cyclone V devices don't have DPA.

Thanks.