Cyclone V LVDS_Rx input clk

Hello I am doing a similar design but with four ADCs and in a Cyclone 3.

However I am confused about the LVDS clock signal input: are all the input clock IO pins dedicated LVDS? I do not want to have problems about clock mismatches so I need to confirm the IO input clock pin is LVDS compatible, no emulated? I know that for transmitters the question is different but for receivers I didn't find any information.

Thanks in advance.

Regards