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Honored Contributor
Honored ContributorCyclone V LVDS_Rx input clk
hi, I am working with Cyclone V to receive high rate data from ADC,the clock from ADC is 500MHz, but the LVDS_rx input clock(f hsclkin on datasheet）can only be 437.5MHz.and then, When i ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes. Which data rate do you try to achieve 1000 MHz DDR or 500 MHz SDR? --- Quote End --- Thanks. I need to receive data 500Mbps, so now the clock coming into Cyclone V must be 250MHz. In addition, can cyclone V receive these data correctly without DPA? Looking forward your advice.
