Forum Discussion
4 Replies
- hsyn
New Contributor
In the "Cyclone V Hard Processor System Technical Reference Manual" PDF, there is a sample code provided for testing SDRAM with the preloader.
I have attached the image below.
When I executed this code, I encountered a verification error. Upon inspecting the code, it seems that they might have incorrectly incremented the "cnt" value in the "read" and "write" loops.
It worked correctly when I modified the "for" loop in the "read" section to be "cnt++".
Is it normal to have errors in the code provided in the PDF, or am I misinterpreting certain parts of it? - aikeu
Regular Contributor
Hi ieeeHuseyin,
I do not fully understand the test algorithment yet. Anyway the cnt = cnt++ seems like not right to me as well. The process of writing data_temp(Rotate_Right) should be the same as the process to compared with expected_data(Rotate_Right).
If you can oberve the same writen memory status pattern as shown in the expected example results in the document then I think it should be correct.
Thanks.
Regards,
Aik Eu
- aikeu
Regular Contributor
Hi ieeeHuseyin,
I will close this thread if no further question.
Thanks.
Regards,
Aik Eu
- aikeu
Regular Contributor
Hi ieeeHuseyin,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
Thanks.
Regards,
Aik Eu