Cyclone V E Development Kit failed on Active Serial Configuration via JTAG

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Hi Guys,

I don't know if the problem was solved.

I had the same one and I solved it.

The MAX V controller doesn't allow to write the EPCQ with the jtag connector.

First you should set the switches to tell you are using the AS.

Second you should rework the resistors R16 to R18 and R22 to R23.

Then you should reprogram the MAX V to inhibit the PFL but only the outputs to the FPGA config inputs. You can use the source code provides with the kit.

It' is a shame that Altera doesn't explain this in the documentation and hasn't developed a pof to correct the problem.

Now I cant write a jic to the EPCQ.

And it works.

I'haven't gone deeper yet but these actions inhibit the embeded blaster II. I think it should be a clock problem, but for my personal use the embeded blaster II is useless.

I will post a solution if i have enought time.

Regards every body.

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Yeap, the resistors rework should work as I told earlier if look at the datasheet connection, just that I do not have the board, but it shouldn't be an issue.

Hi Guys,

I don't know if the problem was solved.

I had the same one and I solved it.

The MAX V controller doesn't allow to write the EPCQ with the jtag connector.

First you should set the switches to tell you are using the AS.

Second you should rework the resistors R16 to R18 and R22 to R23.

Then you should reprogram the MAX V to inhibit the PFL but only the outputs to the FPGA config inputs. You can use the source code provides with the kit.

It' is a shame that Altera doesn't explain this in the documentation and hasn't developed a pof to correct the problem.

Now I cant write a jic to the EPCQ.

And it works.

I'haven't gone deeper yet but these actions inhibit the embeded blaster II. I think it should be a clock problem, but for my personal use the embeded blaster II is useless.

I will post a solution if i have enought time.

Regards every body.

Hi John,

Since the EPCQ device is connected to the MAX V system controller, I think the MAX V doesn't allow user to access the EPCQ device. This is documented for the Cyclone V GT Development kit here https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02112014_88.html

You may need to modify the MAX V image to gain access to the EPCQ device. I suggest you contact Altera support and confirm if you need to do it as mentioned in the link above. If this is not the case, you could also ask them how you can program the EPCQ thats on your V E Kit.

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Hi John,

Well, as per checked thoroughly in datasheet, it never written any way of JTAG to program EPCQ, it writen only EPCQ is programmed through 6 pin AS header. And this means through 6 pin header will be using sof or pof file. Besides, jic file=JTAG indirect programming, and not applicable to load jic while connecting that 6 pin AS header.

Also, JTAG in datasheet shows only connected to flash P30 family memory and not EPCQ.

So, it is not supported in this dev kit officially. Manual rework of connecting resistor can be done as per follow the datasheet, but nothing exact connection is given. That 10k resistor is built on board for nstatus, nconfig, and config_done so no need to connect it is correct.

You may try pof file through JTAG port for EPCQ and share the result as I do not have access to that board.

Sincerely hope you can get back to reply as soon you see this. Was trying to help you

Many thanks.

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.pof file is used for flash, it's not for AS programing. I tried it but it doesn't work out.

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Hi,

I do not program EPCQ directly. I program it via JTAG connection. If I pick the Active Serial Programming, it won't work, I tried it and it doesn't work.

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Hi John,

Well, as per checked thoroughly in datasheet, it never written any way of JTAG to program EPCQ, it writen only EPCQ is programmed through 6 pin AS header. And this means through 6 pin header will be using sof or pof file. Besides, jic file=JTAG indirect programming, and not applicable to load jic while connecting that 6 pin AS header.

Also, JTAG in datasheet shows only connected to flash P30 family memory and not EPCQ.

So, it is not supported in this dev kit officially. Manual rework of connecting resistor can be done as per follow the datasheet, but nothing exact connection is given. That 10k resistor is built on board for nstatus, nconfig, and config_done so no need to connect it is correct.

You may try pof file through JTAG port for EPCQ and share the result as I do not have access to that board.

Sincerely hope you can get back to reply as soon you see this. Was trying to help you

Many thanks.

Hi,

I do not program EPCQ directly. I program it via JTAG connection. If I pick the Active Serial Programming, it won't work, I tried it and it doesn't work.

Hi,

It seems that your board has these already in place. Then I suggest you change the SW switch settings to reflect the AS mode. From the image you posted earlier, I see that the programming mode is in JTAG and not AS (note the JTAG signal chain TDI/ TDO). You need to change this mode to Active Serial in the upper right corner of the Programmer window. This will probably clear out the devices listed . You will have to add the EPCQ device again after changing the Programming mode. After the device is added successfully, select your .jic file and then the Erase, Program and Verify options and proceed. It should work this time.

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Hi John,

Please refer to the following manual for the Cyclone V E Dev Kit :

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cve_fpga_dev_board.pdf

The following is taken from the Cyclone V E kit manual:

https://www.alteraforum.com/forum/attachment.php?attachmentid=14427

What this means is that, to use EPCQ device , you may have to rework the board with 10K resistors as shown in the figure. Before proceeding , please check your board if this configuration is already present. If so, then you just need to modify the SW settings and try. If not, then you need to get 10K resistors and wire the respective signals as shown in the schematic, change the SW settings and then try.

-Abr

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10K resistor is on the board. The problem is I kept failing programing the EPCQ Device by .jic file.

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Hi John.

1. Make sure there are these three documents, schematic="C5E_DEV_KIT_B", Userguide="ug_cve_fpga_dev_kit", Manual="rm_cve_fpga_dev_board".

2. By default, this board support Fast Passive Parallel(FPP), sw1 from MSEL0 until MSEL4 equate to 0000. 0 means it is grounded, understand the schematic, it is at pg8 of schematic.

https://alteraforum.com/forum/attachment.php?attachmentid=14431&stc=1

3. Why set 0000 at FPP which is default?

Kindly study and understand, an example of one of the MSEL switch is given:

Referring MSEL2 set to 0, it is using Flash. Flash(P30) means parallel programming. EEPROM(EPCS or EPCQ) means serial programming. This is the naming system, Flash=parallel, EEPROM=serial. Similarly, info MSEL0 is connected to MAX V can be found and so on.

4. Look at "rm_cve_fpga_dev_board" pg23, program using EPCQ, original text from that page has given the info, "In order to set the configuration scheme to AS mode, resistor rework needs to be done." Resistor rework=add resistor to the 3.3V that are applied to the MSEL0 till MSEL4 when dip switch is at 1111.

4a. This means user have to change the original grounded MSEL0 until MSEL4 into powered by 3.3V Vccpgm, but do not connect 3.3V directly and must connect 1kohm resistor to it. Use the breadboard to connect the 1kohm resistor. From basic electronics, that 1kohm is used to lower the current flow and help dispense heat in FPGA.

4b. This is simplified as it can be, do not skip resistor and direct put 3.3V to MSEL, it will damage the board through high current inrush, in this modifying case, it is not recommended for new learner unless user know how to modify connection.

Last edited to grammar, remove all personal pronouns(I, You, We, They, etc), and picture into attachment.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

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For MSEL is just for telling the FPGA Cyclone V know where will it load the configuration file. My problem right now is programing the ECPQ256. I have attached picture of error

https://www.alteraforum.com/forum/attachment.php?attachmentid=14437

Hi John,

Please refer to the following manual for the Cyclone V E Dev Kit :

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cve_fpga_dev_board.pdf

The following is taken from the Cyclone V E kit manual:

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By default, this board has a FPP configuration scheme setting. In order to set the configuration scheme to AS mode, resistor rework needs to be done.

Configure the MSEL setting using the MSEL DIP switch (SW1) to change the configuration scheme.

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https://www.alteraforum.com/forum/attachment.php?attachmentid=14427

What this means is that, to use EPCQ device , you may have to rework the board with 10K resistors as shown in the figure. Before proceeding , please check your board if this configuration is already present. If so, then you just need to modify the SW settings and try. If not, then you need to get 10K resistors and wire the respective signals as shown in the schematic, change the SW settings and then try.

-Abr