Cyclone V E Development Kit failed on Active Serial Configuration via JTAG

Hi Jhon,

You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header.

You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Hi,

Make sure the jumpers shown below are configured in the factory default settings:

https://www.alteraforum.com/forum/attachment.php?attachmentid=14406

https://www.alteraforum.com/forum/attachment.php?attachmentid=14407

https://www.alteraforum.com/forum/attachment.php?attachmentid=14408

https://www.alteraforum.com/forum/attachment.php?attachmentid=14409

Put these DIP switches in the factory defaults as shown above and then try configuring the FPGA. It should work.

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Hi Jhon,

You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header.

You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage.

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I did indirect programing using .jic file. I use development board kit. I do not design PCB board for FPGA.

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Hi,

Make sure the jumpers shown below are configured in the factory default settings:

https://www.alteraforum.com/forum/attachment.php?attachmentid=14406

https://www.alteraforum.com/forum/attachment.php?attachmentid=14407

https://www.alteraforum.com/forum/attachment.php?attachmentid=14408

https://www.alteraforum.com/forum/attachment.php?attachmentid=14409

Put these DIP switches in the factory defaults as shown above and then try configuring the FPGA. It should work.

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Follow the reference manual for development board kit, the factory default setting is for FPP Configuration, it's not for AS configuration. I have tried all combination of MSEL[4-0], it doesn't work for any combination setting.

1. Yes, all steps in youtube you followed is correct, just need change the option epcs128 to epcq256.

2. Wrong, cyclone v and cyclone v e have different handbook, and you are referring https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf

pg239 table 7-2 is Cyclone V.

2a. Correct handbook for Cyclone V E is https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pdf. Refer pg12 and pg13 for your msel pin. They involve only 4 MSEL switches for sw1(MSEL) + sw2(JTAG chain) + sw3(user dip) + sw4(board setting)

3. "Can't recognize silicon ID for device 1" means you choosing EPCS instead of EPCQ. Please take note.

4. Correct, you are using JTAG and serial configuration, default MSEL is FPP, therefore cannot use default dip switch.

5. SW1 you will confuse because handbook not provided the serial configuration pin, you may refer schematic which is inside the kit as zip in https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html. I hereby summarize for easier option.

5a. MSEL0=connected to T8 pin=ddr3 or Max V. Example MSEL0=1=Off=disable connection to Max V and DDR3.

MSEL1=connected to P9 pin=ddr3 or Max V.

MSEL2=connected to G5 pin=Flash P30(for parallel memory) or Max V or Max II power or uC

MSEL4=connected to M7 pin=ddr3 or or Max V

DDR3=U7(look on your board labeled)=JTAG blaster TDI

W9 pin=TDO of JTAG.

5b. If you are using EPCQ256 and JTAG, sw1 shall be somewhere 0010 through Max V and resistor rework or 1111 bypass Max V and resistor rework, for sw2 3 4, please study it correctly, fan on/off or Max V enable/disable or etc, everything is there in handbook pg12 pg13 given.

Edited link missing, the method to post link upgraded during I post this.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

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1. Yes, all steps in youtube you followed is correct, just need change the option epcs128 to epcq256.

2. Wrong, cyclone v and cyclone v e have different handbook, and you are referring https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf

pg239 table 7-2 is Cyclone V.

2a. Correct handbook for Cyclone V E is https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pdf. Refer pg12 and pg13 for your msel pin. They involve only 4 MSEL switches for sw1(MSEL) + sw2(JTAG chain) + sw3(user dip) + sw4(board setting)

3. "Can't recognize silicon ID for device 1" means you choosing EPCS instead of EPCQ. Please take note.

4. Correct, you are using JTAG and serial configuration, default MSEL is FPP, therefore cannot use default dip switch.

5. SW1 you will confuse because handbook not provided the serial configuration pin, you may refer schematic which is inside the kit as zip in https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html. I hereby summarize for easier option.

5a. MSEL0=connected to T8 pin=ddr3 or Max V. Example MSEL0=1=Off=disable connection to Max V and DDR3.

MSEL1=connected to P9 pin=ddr3 or Max V.

MSEL2=connected to G5 pin=Flash P30(for parallel memory) or Max V or Max II power or uC

MSEL4=connected to M7 pin=ddr3 or or Max V

DDR3=U7(look on your board labeled)=JTAG blaster TDI

W9 pin=TDO of JTAG.

5b. If you are using EPCQ256 and JTAG, sw1 shall be somewhere 0010 through Max V and resistor rework, for sw2 3 4, please study it correctly, everything is there in handbook pg12 pg13 given.

Edited link missing, the method to post link upgraded during I post this.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

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Hi @Tzi Khang,

Your info makes me more confusing. The link https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pdf is the user guide of Cyclone V E Development Kit, it's not handbook. In this guide, it doesn't talk much about how to set up MSEL. I have tried MSEL[4-0] 0010 but it failed at 99% or 98%. It drives me nut.

I selected EQCQ256 in Device and Pin option. Have you tried your method on Cyclone V E Development board and get it compile successfully? I am newbie, so I don't know much about this process.

Using dev kit, just refer to the given user guide and manual and schematic you will be fine. Do not go and look for Cyclone V handbook, it makes you confuse.

https://www.alteraforum.com/forum/attachment.php?attachmentid=14417

Resistor rework means, please go and find 1k resistor and put to them connected to Vccpgm.

Since you are beginner, use the 1111 and bypass Max V configuration.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

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Using dev kit, just refer to the given user guide and manual and schematic you will be fine. Do not go and look for Cyclone V handbook, it makes you confuse.

https://alteraforum.com/forum/attachment.php?attachmentid=14417&stc=1

Resistor rework means, please go and find 1k resistor and put to them connected to Vccpgm.

Since you are beginner, use the 1111 and bypass Max V configuration.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

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I don't understand "please go and find 1k resistor and put to them connected to Vccpgm". What do you mean about it? Does it mean that I just need to change the Sw1 combination. I have tried combination "1111", but it doesn't work. Is there any other thing I missing in configuration process? If you are successful to program it, what MSEL combination did you use?

Hi John.

1. Make sure there are these three documents, schematic="C5E_DEV_KIT_B", Userguide="ug_cve_fpga_dev_kit", Manual="rm_cve_fpga_dev_board".

2. By default, this board support Fast Passive Parallel(FPP), sw1 from MSEL0 until MSEL4 equate to 0000. 0 means it is grounded, understand the schematic, it is at pg8 of schematic.

https://alteraforum.com/forum/attachment.php?attachmentid=14431&stc=1

3. Why set 0000 at FPP which is default?

Kindly study and understand, an example of one of the MSEL switch is given:

Referring MSEL2 set to 0, it is using Flash. Flash(P30) means parallel programming. EEPROM(EPCS or EPCQ) means serial programming. This is the naming system, Flash=parallel, EEPROM=serial. Similarly, info MSEL0 is connected to MAX V can be found and so on.

4. Look at "rm_cve_fpga_dev_board" pg23, program using EPCQ, original text from that page has given the info, "In order to set the configuration scheme to AS mode, resistor rework needs to be done." Resistor rework=add resistor to the 3.3V that are applied to the MSEL0 till MSEL4 when dip switch is at 1111.

4a. This means user have to change the original grounded MSEL0 until MSEL4 into powered by 3.3V Vccpgm, but do not connect 3.3V directly and must connect 1kohm resistor to it. Use the breadboard to connect the 1kohm resistor. From basic electronics, that 1kohm is used to lower the current flow and help dispense heat in FPGA.

4b. This is simplified as it can be, do not skip resistor and direct put 3.3V to MSEL, it will damage the board through high current inrush, in this modifying case, it is not recommended for new learner unless user know how to modify connection.

Last edited to grammar, remove all personal pronouns(I, You, We, They, etc), and picture into attachment.

Best Regards,

Tzi Khang, Lim

(This message was posted on behalf of Intel Corporation)

Hi John,

Please refer to the following manual for the Cyclone V E Dev Kit :

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cve_fpga_dev_board.pdf

The following is taken from the Cyclone V E kit manual:

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By default, this board has a FPP configuration scheme setting. In order to set the configuration scheme to AS mode, resistor rework needs to be done.

Configure the MSEL setting using the MSEL DIP switch (SW1) to change the configuration scheme.

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https://www.alteraforum.com/forum/attachment.php?attachmentid=14427

What this means is that, to use EPCQ device , you may have to rework the board with 10K resistors as shown in the figure. Before proceeding , please check your board if this configuration is already present. If so, then you just need to modify the SW settings and try. If not, then you need to get 10K resistors and wire the respective signals as shown in the schematic, change the SW settings and then try.

-Abr