Honored Contributor
Honored Contributor1. Yes, all steps in youtube you followed is correct, just need change the option epcs128 to epcq256.
2. Wrong, cyclone v and cyclone v e have different handbook, and you are referring https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf pg239 table 7-2 is Cyclone V. 2a. Correct handbook for Cyclone V E is https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pdf. Refer pg12 and pg13 for your msel pin. They involve only 4 MSEL switches for sw1(MSEL) + sw2(JTAG chain) + sw3(user dip) + sw4(board setting) 3. "Can't recognize silicon ID for device 1" means you choosing EPCS instead of EPCQ. Please take note. 4. Correct, you are using JTAG and serial configuration, default MSEL is FPP, therefore cannot use default dip switch. 5. SW1 you will confuse because handbook not provided the serial configuration pin, you may refer schematic which is inside the kit as zip in https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html. I hereby summarize for easier option. 5a. MSEL0=connected to T8 pin=ddr3 or Max V. Example MSEL0=1=Off=disable connection to Max V and DDR3. MSEL1=connected to P9 pin=ddr3 or Max V. MSEL2=connected to G5 pin=Flash P30(for parallel memory) or Max V or Max II power or uC MSEL4=connected to M7 pin=ddr3 or or Max V DDR3=U7(look on your board labeled)=JTAG blaster TDI W9 pin=TDO of JTAG. 5b. If you are using EPCQ256 and JTAG, sw1 shall be somewhere 0010 through Max V and resistor rework or 1111 bypass Max V and resistor rework, for sw2 3 4, please study it correctly, fan on/off or Max V enable/disable or etc, everything is there in handbook pg12 pg13 given. Edited link missing, the method to post link upgraded during I post this. Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)
