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BrianSune_Froum's avatar
BrianSune_Froum
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5 months ago
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Cyclone V custom board VCCIO puzzling behavior

Dear Intel and all,

I am working on Cyclone V soc 5CSEBA5U19C8N.
There is a very puzzling VCCIO behavior.
According to "Cyclone® V Device Family Pin Connection Guidelines
PCG-01014-3.2".

Any 3.0 below VCCIO must use a VCCPD with 2.5V.
I am supplying VCCIO of bank 3B+4A with VCCPD 2.5V and the VCCIO is using 1.2V.
However when measuring the VCCIO rail the voltage raised to almost 1.5V.

Before the FPGA chip is applied the voltage rail is able to measure clean 1.2V which eliminates the DCDC issue.

This is very puzzling, please FAE or Intel employee support.

Thank you

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  • BrianSune_Froum's avatar
    BrianSune_Froum
    5 months ago

    There are new measured data.

    If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
    But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
    So there are some leakage current inside the diode path? from VCCPD to VCCIO?

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  • BrianSune_Froum's avatar
    BrianSune_Froum
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    4 months ago

    @FvM

    I do think this is common.

    For example Kintex 7 one IO bank is completely empty on any load yet there are no such thing happened.
    I think this is the inherent silicon design fault on Altera FPGA.


    First got to understand the VCCPD and VCCIO what actually means rather than guessing diode etc.

    https://www.intel.com/content/www/us/en/support/programmable/support-resources/power/pow-overview.html

    I don't think the leak could introduce such result.

    1.2 to 1.5 is 300mV can't explain how could it reach that level.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    4 months ago

    Hi,
    I understand that the effect is unexpected. However VCCIO supply of most FPGA boards will absorb uA range leakage currents unnoticed, thus it might be that observed VCCD to VCCIO leakage current is quite common.

    Regards
    Frank

  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    4 months ago

    @FvM

    I am afraid even with more board had assemble the same issue are kept. without any load aka resistor or other IO driver sink/source from any pins. There is always a raise voltage on 1.2V VCCIO /w VCCPD 2.5V from 1.2V to 1.45

  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    5 months ago

    There are new measured data.

    If I attached a simple 10k resistor to the 1.2V rail. it will drop back to normal 1.2 range.
    But the loaded /w 10k is still measuring 40mV higher than unloaded DCDC w/o the FPGA chip.
    So there are some leakage current inside the diode path? from VCCPD to VCCIO?

    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor
      5 months ago
      Hi,
      result sounds promising, a lower pull-down value like 500R or 1k can hopefully cut unwanted VCCIO leakage. I'd however expect a statement from Intel support, it might be a known problem. Particularly we should get specification of maximal leakage current.

      A final question, can you exclude that the problem is caused by a partly damaged device, e.g. due to ESD?
      • BrianSune_Froum's avatar
        BrianSune_Froum
        Icon for Contributor rankContributor
        5 months ago

        No this theory don't holds. If it is damaged by ESD why only 1.2V is able to trigger a higher voltage?
        I will highly expected :
        A internal VCCPD diode is leakage due to VCCIO-VCCPD high at VCCIO low.
        As V(diode) breakdown aka current increase when voltage increase aka basic diode IV model.
        However if a ESD had break the barrier then no matter it is what voltage level.

        I do measured via diode model on meter and all VCCPD and VCCIO related group is almost same.

        The data last I got is that around 100uA to 1mA on VCCIO rail can easily remove the voltage increase behavior.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    5 months ago

    Hi,
    I designed with Cyclone V nine years ago but don't remember a similar issue.

    Is VCCIO 1.2V node completely floating or has it relevant load? Presumed it's true that Cyclone V is actually driving out on VCCIO due to VCCPD leakage current and not powered by a different path, I would try to determine the actual leakage current, both for nominal 1.2V and 0V level. There's no leakage specification in datasheet, I would not exclude a small leakage current, e.g. below one or maximal a few mA which could be easily dropped by a pull-down resistor.

    Of course, if such effects exists, they should be mentioned in datasheet and user manual.

    Regards
    Frank

    • BrianSune_Froum's avatar
      BrianSune_Froum
      Icon for Contributor rankContributor
      5 months ago

      First you mentioned you had design Cyclone V before.
      I make the following assumptions that should make sense and should "NOT" be violate the device inherent silicon design.

      1) according to handbook:
      In the Cyclone V devices, all I/O banks have individual VCCPD with the following exceptions:
      • Cyclone V E, GX and GT devices:
      • Banks 1A (if available) and 2A share the same VCCPD.
      • Banks 3B and 4A share the same VCCPD.
      • Banks 7A and 8A share the same VCCPD.
      • Cyclone V SE, SX and ST devices:
      • Banks 1A (if available) and 2A share the same VCCPD.
      • Banks 3B and 4A share the same VCCPD.
      • Banks 6A and 6B share the same VCCPD.

      So the rules should follow VCCPD = 2.5V if VCCIO <= 2.5V else VCCPD === VCCIO

      2) the same puzzling bank is tested with 1.8V 2.5V which shows no such behavior on the same gear.

      3) So if VCCPD is causing such issue why 1.8V is not having such behavior? aka increase on voltage.