CYCLONE V - HPS and I2C Peripheral Pin

Hi

Any update on this case?

Did adding a pull up resistor solved the issue?

Regards

Jingyang, Teh

I tried both with external Pull-Up resistors (included in the client) and adopting PU in the pads, but the result is the same.
However please note my previous messages concerning the different behavior of the different peripherals i2c0 and i2c1 !

Hi Stefano

Thanks for your testing.

After discussing we are suspecting either it is the i2c hard IP or the HPS-to-FPGA interface that could be the problem.

Below is the data flow of the signal.

Bolded are the part that we are currently suspecting.

HPS I2C Hard IP >> HPS-to-FPGA interface >> FPGA fabric >> FPGA I/O >> Level Shifter >> I2C slave

Is it possible if you could SignalTap the signals of the i2c signals for the setup you have for i2c0 and i2c1?

i2c1_out_scl

i2c1_out_sda

i2c1_in_scl

i2c1_in_sda

arm_a9_hps_i2c1_out_data

arm_a9_hps_i2c1_sda

arm_a9_hps_i2c1_clk_clk

arm_a9_hps_i2c1_scl_in_clk

GP0GPIO[0]

GP0GPIO[1]

Regards

Jingyang, Teh

In addition, regarding interface I2c0, signals does not seem accessible fron Signal Tap (since they do not share FPGA Fabric)
But however in such a case the interface in these conditions works pretty well !

Hi Stefano

From the signal tap pictures that you send it seems like the problem could due to be originating between the HPS I2C Hard IP and HPS-to-FPGA interface.

This is not fixable by any software patch at the moment if the problem is coming from the HPS I2C Hard IP to the FPGA interface.

HPS I2C Hard IP >> HPS-to-FPGA interface >> FPGA fabric >> FPGA I/O >> Level Shifter >> I2C slave

Are you seeing this behavior on other boards as well?

Regards

Jingyang, Teh

Hi Stefano

Do you have an update for this?

Any chance that you are seeing this behavior on other boards as well?

Regards

Jingyang, Teh

Hi Stefano

Please bear with me while I discuss with the engineering team.

Regards

Jingyang, Teh

Hi Stefano

Due to the year end festivals, a lot of my colleagues are on leave hence the slow response.

Sorry, I still got no update on this case as of now.

Regards

Jingyang, Teh

Hi Stefano

There is an internal case number that was created to track this issue.( 15014617860 )

The engineering team will be taking a look at this. They will not be able to provide a patch anytime soon.

Is it okay if we close this case since that the HPS i2c Signal is okay when it is on the dedicated IO instead of through the FPGA fabric?

Regards

Jingyang, Teh

Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Regards

Jingyang, Teh