CYCLONE V - HPS and I2C Peripheral Pin

Hi Stefano

Thanks for your testing.

After discussing we are suspecting either it is the i2c hard IP or the HPS-to-FPGA interface that could be the problem.

Below is the data flow of the signal.

Bolded are the part that we are currently suspecting.

HPS I2C Hard IP >> HPS-to-FPGA interface >> FPGA fabric >> FPGA I/O >> Level Shifter >> I2C slave

Is it possible if you could SignalTap the signals of the i2c signals for the setup you have for i2c0 and i2c1?

i2c1_out_scl

i2c1_out_sda

i2c1_in_scl

i2c1_in_sda

arm_a9_hps_i2c1_out_data

arm_a9_hps_i2c1_sda

arm_a9_hps_i2c1_clk_clk

arm_a9_hps_i2c1_scl_in_clk

GP0GPIO[0]

GP0GPIO[1]

Regards

Jingyang, Teh