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Altera_Forum's avatar
Altera_Forum
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12 years ago

Cyclone-IV E USB Blaster JTAG header VCC(TRGT)

Dear sir,

I am using cyclone -IV E FPGA in JTAG chain.

I don't have free pins on JTAG header on the board to connect, 2.5V to pin number 4 of USB blaster cable.

Can I connect 3.3V to pin number 4(VCC(TRGT) of USB blaster as 3.3V is already available in JTAG header ?

I am using 20 pin connector to connect a. Board RS232 links b. JTAG programming of non-altera devices c. JTAG debuggers for debugging MIPS processor and so on.

Please find the attachment of 20 pin JTAG connector and the signals.

Please clarify.

Regards,

Thulasi

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Pin 4 of the JTAG header is used to power circuitry in the USB-Blaster. This voltage determines the voltage at which the JTAG signals are driven to the target.

    The USB-Blaster will happily operate at 3.3V. however, JTAG in Cyclone IV devices is designed to operate at 2.5V. So, doing this will result in you over driving the device's JTAG signals. It'll probably work for a while but is clearly not recommended and may well kill your device.

    You have 3.3V available. Can you regulate this down to 2.5V externally? You clearly must have some external breakout board/cable to which you connect your USB-Blaster. It would only take a tiny 3-pin LDO regulator.

    The current consumed by the USB-Blaster is very low - datasheet states 10mA max. In practice it's nearer 1mA. So, I suspect you may even be able to drop the voltage accurately enough with a couple of resistors...
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    In cyclone IV FPGA, all JTAG signals are in Bank 1. I am connecting VCCIO of bank1 to 3.3V power supply.

    Please clarify whether the JTAG signals from Bank1 are 2.5V complaint or 3.3V complaint ?

    Regards,

    Thulasi
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Please see the response from mysupport link in Altera website....

    "Sorry for not explaining in details. By providing 3.3V to pin-4 of JTAG port, you will not be damaging the FPGA device FPGA pin since the bank 1 is powered up using 3.3V power supply. In other words, bank 1 will be using 3.3V IO standard during configuration.

    The main reason that the configuration chapter is using 2.5V is due to if you are using USB-Blaster rev A or rev B cable then you will need to have pin-4 connect to 2.5V. If pin-4 is connected to 3.3V for rev A or rev B USB-Blaster then you will damage the cable. If you are using USB-Blaster rev C then you will not face any issue in using 2.5V or 3.3V to pin-4 JTAG port."

    I hope i can connect 3.3V JTAG signals from USB blaster to cyclone-IV E FPGA on the board.

    Please comment on the above response from Altera.

    Regards,

    Thulasi
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I'm not going to take issue with such an answer from Altera. However, I will continue to design to the documentation Altera provide for their parts.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I'm not convinced the document addresses that. Table 2-4 (on page 2-5) doesn't distinguish between A & B or C cables and implies it's perfectly OK to power any of the cables to 5V...

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    Sorry for not providing the detail information that i got from Altera....... The following is the statement from Altera....

    "There is no problem in using VccTRGT for all USB-Blaster revision. The only concern is for Rev A and Rev B USB-Blaster which when the VccTRGT(pin no. 4) = 2.5V and VccIO = 3.3V then this will damage the USB-Blaster since it couldn't handle the over-voltage stress. " ....

    Hope i can connect

    1. 3.3V to VCC(TRGT) of USB blaster.

    2. I can connect FPGA also in 3.3V complaint JTAG chain in the board.

    But, still i am worried about your response......

    " However, JTAG in Cyclone IV devices is designed to operate at 2.5V. So, doing this will result in you over driving the device's JTAG signals. It'll probably work for a while but is clearly not recommended and may well kill your device. "

    Please clarify..

    Regards,

    Thulasi
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    If Altera are stating that the only risk of driving the USB-Blaster with 3.3V is to the rev A/B Blasters and not to the FPGA, then I'd be comfortable with that. However, as I've already stated, I will continue to design my boards to the documentation Altera release for their parts.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    In my experience, Rev. B Blasters had no issues with 3.3V. There is however a known issue with Rev. C Blasters regarding the order of applying power to the target and USB port (see the respective errata sheet and/or note on page 1-3 in the Blaster datasheet).

    Shameless plug: Our EEBlaster (http://www.entner-electronics.com/tl/index.php/eeblaster.html) has none of this issues...

    In my opinion 3.3V can be used for JTAG, however there is a lower margin for overshoots then (this applies to all I/Os but might be especially critical for the JTAG lines which typically go of board, i.e. long lines and may be hot plugged). See also: http://www.altera.com/literature/hb/cyclone-iv/cyiv-51008.pdf, page 5 (from the center of the page...). I assume that this is the background of the 2.5V recommendation for pin 4 from Altera. So you should ensure that there is no overshooting above 4.1V at the FPGA side, e.g. by series resistors and/or clamping diodes (but JTAG clock quality should also not be degraded too much, of course).

    In some of our products we use Cyclone IV with 3.3V JTAG voltage and 100R on each JTAG-line which are working without issues (at least together with our EEBlaster).

    Regards,

    Thomas

    www.entner-electronics.com - Home of EEBlaster (EUR 49,-)