Cyclone IV E – PLL Power Track Width Recommendation Clarification

Hi, thanks for your response.

In our design, the maximum clock frequency is 33 MHz, and the FPGA uses a 1 mm ball‑pitch package. Due to this, we are able to route the PLL net using a 20 mil trace width after the filtering section.

From the filter output up to the FPGA cut‑out, the trace width remains at 20 mil.
Inside the cut‑out, from the cut‑out region to the FPGA ball, the trace width is reduced to 6 mil to meet the package escape routing constraints.

Regards,

Yogesh