Forum Discussion
YogeshaDG
New Contributor
New ContributorCyclone IV E – PLL Power Track Width Recommendation Clarification
Hi, I am working on a design that uses the Cyclone IV E FPGA, and I’ve been following the Altera/Intel board design guidelines for PLL power routing. The document recommends using a minimum 20 mil t...
YogeshaDGNew Contributor
New ContributorHi, thanks for your response.
In our design, the maximum clock frequency is 33 MHz, and the FPGA uses a 1 mm ball‑pitch package. Due to this, we are able to route the PLL net using a 20 mil trace width after the filtering section.
From the filter output up to the FPGA cut‑out, the trace width remains at 20 mil.
Inside the cut‑out, from the cut‑out region to the FPGA ball, the trace width is reduced to 6 mil to meet the package escape routing constraints.
Regards,
Yogesh
Farabi_Altera
Regular Contributor
Regular ContributorHello,
Answer provided in previous support.
thanks,
Farabi
