Forum Discussion
Honored ContributorCyclone III AS configuration bizarreness
I am using a cyclone III (EP3C25F324C8N) with an EPCS16 configuration device.
I am programming the configuration device through the FPGA with the serial flash loader. The problem is that the Cyclone III device will not configure itself from the EPCS16. It is stuck in an endless loop of retries UNTIL I MOMENTARILY SHORT THE nSTATUS PIN TO 3.3 VOLTS!!!! (...I discovered this by accident, no grounding the pin doesn't do it.) As soon as I do that the device configures and runs my test program (blinks LEDs). I also tried driving it high momentarily with an 8051 to no avail. Any ideas? Thanks, Rob UPDATE: It also configured when I touched CONF_DONE with a probe. Upon further investigation I found that adding a 100 pF capacitor from CONF_DONE to GND fixes this problem ...no idea why.31 Replies
Altera_ForumNot sure what your circuit looks like, but nSTATUS has to be pulled up to VCCIO (permanently) in order to enter configuration mode. Are you saying that you have to short the pull-up resistor to get the FPGA to configure?
The recommended value for the pull-up is 10k for 3.3V VCCIO.- Altera_Forum
Yes. I have to short the pull-up resistor - briefly. I just tap it with a probe connected to 3.3V and it works great.
The resistor is a 10K to 3.3 V. - Altera_Forum
My guess is that the device is getting some sort of configuration error... either a bad check sum or something... and asserting nSTATUS low to report the error. When I touch the nSTATUS pin to 3.3V it is being seen (by a separate piece of logic in the FPGA) as indicating that configuration did not have an error so the FPGA goes ahead and enters user mode, even though nSTATUS returns to low. Anyway, I suspect that my problem may be in the .JIC file, not the hardware.
Anyone have any experience with this (especially the use of JIC files) ? PS I am using Quartus V7.1 - Altera_Forum
Is this a custom board or are you testing on a development kit? If it's a custom board, have you applied the MSEL pins workaround in the ciii errata sheet (http://altera.com/literature/ds/es_cyciii.pdf)?
Wrong config scheme selected at startup can cause problems like yours. - Altera_Forum
It is a custom board.
The MSEL pins are connected directly to either V3.3 (supplied by a high current bench supply) or GND. - Altera_Forum
Rob,
Did you ever find the root of your problem? I am experiencing a similar behaviour. It is on a custom board based with a Cyclone I, 1C20 device. I am using the CFI flash/CPLD-based configuration controller reference design. I, too, am having an intermittent configuration issue which disappears when probing with a standard 10X scope probe or a logic analyzer probe. The problem reappears when using a FET probe with <1pF capacitance. I started a service request regarding this issue but have received no useful information. Thanks, steve - Altera_Forum
Not really but here's the latest theory: Apparently there's some sort of race condition in the Cyclone 3's configuration circuitry. I mistakenly used 3.3V for the configuration voltages but the specification is for these signals (nStatus, COMF_DONE, nCONFIG, DATA1, DCLK, nCSO, ASD)) to be driven by (or pulled up to) a 2.5V standard. This may have contributed to the timing problem.
When I spin the board I'll fix the voltage AND add the capacitor; then, hopefully, I'll see what's what. - Altera_Forum
I've had a similar problem myself with an EPCS16 and Cyclone III. It wasn't configuring so I probed the DCLK pin with a scope and it configured. Then I found that touching the pin with a screwdriver was sufficient for it to configure and if the screwdriver was there on power up then it would also work. Very strange.
Anyway, I added a 100pF capacitor between the DCLK pin and GND and it has been fine since that. If anyone can explain this behaviour to me then please do. I would like to understand what was going on, but it's nice to have resolved the problem even if more by luck than judgement :) - Altera_Forum
Hello,
I didn't yet experience these problems with AS configuration but I guess it could be due to a ringing DCLK. What's the distance between FPGA and EPCS and to the AS programming connector or any other devices connected to DCLK? Although the 100 pF may help, it seems something brute to me. A DCLK series resistor (~100 ohms) at the FPGA could be a more gentle way to abandon clock ringing, provided a regular digital ground (PCB power plane) exists for the circuit. Regards, Frank - Altera_Forum
Hi Frank,
Are you suggesting that ringing on DCLK could be being interpreted as extra clock edges? There is 30mm between FPGA and EPCS - no other devices are connected to DCLK. There is a ground layer and a 3V3 layer on the PCB. Adding a series resistor isn't as easy to implement in practice but I will give it a try. I suppose that if the scope is affecting the amount of ringing then it will be difficult to see the difference between a series R and the 100pF to GND accurately. Thanks for your help.
