Cyclone III AS configuration bizarreness

Hi Frank,

Are you suggesting that ringing on DCLK could be being interpreted as extra clock edges?

There is 30mm between FPGA and EPCS - no other devices are connected to DCLK. There is a ground layer and a 3V3 layer on the PCB.

Adding a series resistor isn't as easy to implement in practice but I will give it a try. I suppose that if the scope is affecting the amount of ringing then it will be difficult to see the difference between a series R and the 100pF to GND accurately.

Thanks for your help.