Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHello,
I didn't yet experience these problems with AS configuration but I guess it could be due to a ringing DCLK. What's the distance between FPGA and EPCS and to the AS programming connector or any other devices connected to DCLK? Although the 100 pF may help, it seems something brute to me. A DCLK series resistor (~100 ohms) at the FPGA could be a more gentle way to abandon clock ringing, provided a regular digital ground (PCB power plane) exists for the circuit. Regards, Frank