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Altera_Forum's avatar
Altera_Forum
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10 years ago

Cyclone II LVDS termination on DE2

hey guys,

I the plan is to use the Terasic DE2 LVDS lines to receive serial data from an ADC. The Cyclone II device handbook (figure 11-3) says that the LVDS receiver line should terminate with 100ohm resistor, now on the DE2 board I was wondering if this termination has been taken care of already, I am gessing not since that would make the pin selection less flexible.

If it does need to be terminated with 100ohm resistors, does the diagram attached look like the correct method to achieve this.

http://www.alteraforum.com/forum/attachment.php?attachmentid=10806&stc=1

Thanks very much.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The DE2 board is not really intended for use with LVDS via the GPIO connector. Some of the newer DEx boards are and feature sites for the 100R resistors which, typically, are not fitted. A quick look through the schematics for the DE2 board confirms there aren't any sites for the 100R termination resistors.

    So, without those sites on the board you will have to do something along the lines of your diagram. Alternatively, you could consider soldering resistors directly to the back of the DE2 board where the GPIO connector through hole pins are accessible. The closer to the FPGA the better.

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hey Alex, thanks for that, stuck with the DE2 for now, will have to convince the bosses to invest in a better board after showing some results with the DE2.

    If I go down the soldering 100ohm resistors to the DE2 GPIO pins route (which is distilled genius BTW), another issue that comes to mind is the PCB track length between GPIO and the FPGA. Do you reckon the track lengths are matched for every pin on the header?

    Thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi zoulzubazz,

    Yes, you should ensure trace length are matched to avoid signal integrity issue. You can refer to "Board Design Considerations" section in the CII device handbook, vol 1 -> chapter 11 for further details.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi,

    Just to add that you should take note that with soldered resistor, the signal integrity might not be as good as originally mounted resistor. In case you observe degraded signal integrity, this could be one of the possible root cause during debug.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The DE2 board will not have length matched traces to the GPIO connector by virtue of the fact that's not what it's really intended for. However, it's more important to match the connections to the resistor than to the FPGA. LVDS is a current-mode driver, the 100R resistor completing the current path. The LVDS input buffers at the FPGA are high impedance. So, assuming a relatively modest length connection from ADC to DE2 board (and associated immunity to noise that offers), the only integrity issue you might encounter is what noise the high impedance traces (from resistor to FPGA) pick up. That ain't going to be much.

    Unless you're looking to really push the performance - I suggest you steer well clear of the 805Mbps headline figure for Cyclone II - then I'd suggest you stand a good chance of this working, at least well enough to persuade your boss to buy something more fit for purpose...

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thanks, yes, using a 12bit ADC at clocked between 50MHz to 60MHz which means a data rate between 600Mbps and 720Mbps, guessing this is ok? Shall report back on how i get on.

    Cheers
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    By the way, you can try to perform a signal integrity simulation ie with IBIS model and your planned board setup prior to hardware implementation.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The skew between the traces on the DE2 board shouldn't be enough to cause you trouble at those rates.

    At 720Mbps you've a 1.4ns period. LVDS requires a transition time - the only thing trace length mismatch is going to have a negative impact on - of between 260ps and 0.3 * 1.4ns = 417ps. Typically devices will operate nearer the higher end of that range to keep switching noise to a minimum.

    Trace length mismatch can probably 'eat into' half of that - 417ps/2 (and probably more) - before you notice any adverse effects. That's well over an inch of extra trace on one of the pairs with respect to the other. I'm sure you will be able to find one (or more) pairs that fit that criteria.

    If you do run into trouble reduce the clock rate. You should find the transition times increase and help you out.

    Cheers,

    Alex