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Altera_Forum's avatar
Altera_Forum
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11 years ago

Cyclone II LVDS termination on DE2

hey guys, I the plan is to use the Terasic DE2 LVDS lines to receive serial data from an ADC. The Cyclone II device handbook (figure 11-3) says that the LVDS receiver line should terminate with...
Altera_Forum's avatar
Altera_Forum
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11 years ago

The DE2 board will not have length matched traces to the GPIO connector by virtue of the fact that's not what it's really intended for. However, it's more important to match the connections to the resistor than to the FPGA. LVDS is a current-mode driver, the 100R resistor completing the current path. The LVDS input buffers at the FPGA are high impedance. So, assuming a relatively modest length connection from ADC to DE2 board (and associated immunity to noise that offers), the only integrity issue you might encounter is what noise the high impedance traces (from resistor to FPGA) pick up. That ain't going to be much.

Unless you're looking to really push the performance - I suggest you steer well clear of the 805Mbps headline figure for Cyclone II - then I'd suggest you stand a good chance of this working, at least well enough to persuade your boss to buy something more fit for purpose...

Cheers,

Alex