Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Cyclone II LVDS termination on DE2

hey guys, I the plan is to use the Terasic DE2 LVDS lines to receive serial data from an ADC. The Cyclone II device handbook (figure 11-3) says that the LVDS receiver line should terminate with...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hey Alex, thanks for that, stuck with the DE2 for now, will have to convince the bosses to invest in a better board after showing some results with the DE2.

If I go down the soldering 100ohm resistors to the DE2 GPIO pins route (which is distilled genius BTW), another issue that comes to mind is the PCB track length between GPIO and the FPGA. Do you reckon the track lengths are matched for every pin on the header?

Thanks.