cyclone II : dual port dual clock memory possible?

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There is any workaround to this problem?

Error: M4K memory block WYSIWYG primitive "vram8k:vram8k_inst|altsyncram:altsyncram_component|altsyncram_3s62:auto_generated|ram_block1a0" utilizes the dual-port dual-clock mode. However, this mode is not supported in Cyclone II device family in this version fo Quartus...

I am using Quartus 7.2SP1 Web edition.

I am implementing a soc, and would like to have 2 ports, dual clock video memory.

Thanks

Roni

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I got the same problem, anybody knows how to make it work ? thanks

You have to add a default parameter in Analysis & Synthesis Settings, as described in the Cyclone II Errata Sheet (shown as respective tcl command)

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set_parameter -name CYCLONEII_SAFE_WRITE "\"RESTRUCTURE\""

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The memory consumption is however doubled by this workaround. For known fixed devices, another setting exists.

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You have to add a default parameter in Analysis & Synthesis Settings, as described in the Cyclone II Errata Sheet (shown as respective tcl command)

The memory consumption is however doubled by this workaround. For known fixed devices, another setting exists.

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You're the man. It does work, thanks a lot.