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Altera_Forum
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17 years ago

cyclone II : dual port dual clock memory possible?

There is any workaround to this problem? Error: M4K memory block WYSIWYG primitive "vram8k:vram8k_inst|altsyncram:altsyncram_component|altsyncram_3s62:auto_generated|ram_block1a0" utilizes the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

You have to add a default parameter in Analysis & Synthesis Settings, as described in the Cyclone II Errata Sheet (shown as respective tcl command)

--- Quote Start ---

set_parameter -name CYCLONEII_SAFE_WRITE "\"RESTRUCTURE\""

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The memory consumption is however doubled by this workaround. For known fixed devices, another setting exists.