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Altera_Forum
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18 years ago

cyclone II : dual port dual clock memory possible?

There is any workaround to this problem? Error: M4K memory block WYSIWYG primitive "vram8k:vram8k_inst|altsyncram:altsyncram_component|altsyncram_3s62:auto_generated|ram_block1a0" utilizes the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The error might be related to the M4K issue in the Cyclone II errata sheet. Check the errata sheet to see whether it is OK for your design to use a setting that will let Quartus implement the memory.