Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorcyclone II : dual port dual clock memory possible?
There is any workaround to this problem? Error: M4K memory block WYSIWYG primitive "vram8k:vram8k_inst|altsyncram:altsyncram_component|altsyncram_3s62:auto_generated|ram_block1a0" utilizes the ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- You have to add a default parameter in Analysis & Synthesis Settings, as described in the Cyclone II Errata Sheet (shown as respective tcl command) The memory consumption is however doubled by this workaround. For known fixed devices, another setting exists. --- Quote End --- You're the man. It does work, thanks a lot.
