davekrzy
New Contributor
New ContributorCyclone 10 LP LVDS capability
Can cyclone 10 work with a 250MHz DDR input? LVDS common is 1.25V, differential is 200mV and clock rate is 250 MHz. Thanks.
Forum Discussion
4 Replies
FvMSuper Contributor
Hi,
general answer is yes, Cyclone 10 LP can achieve at least 640 MBPS LVDS data rate (with slowest speed grade), review datasheet.
The question is however no very clear, are you referring to data rate or DDR clock. It's also important to know how the receive clock is provided, e.g. sent to the FPGA along with the data? Extracting clock from received data (CDR) isn't natively supported by Cyclone 10 LP FPGA family.
davekrzyI would be trying to use a receive clock provided to the FPGA along with the data as well as a frame valid signal. I am using the IP core and was wondering how do you define the connection in the vhdl file. Looks like the IP only defines 1 side of the input pin, so do I only need to define 1 pin input at the top level as well?
IP snippet
component LVDS_RX is
port(
rx_in : in std_logic_vector(0 downto 0);
rx_inclock : in std_logic;
rx_out : std_logic_vector(7 downto 0);My top level snippet
entity TopLevel is
port (nrst : in std_logic; -- active losclkin : in std_logic;rx_in_sig : in std_logic;);
end TopLevel;Thanks!
AqidAyman_AlteraRegular Contributor
Hello,
You can refer to the datasheet here on the LVDS specification of Cyclone 10 LP:
LVDS Receiver Timing Specification:
Regards,
Aqid
- AqidAyman_Altera
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