francisco-padilla-ed
New Contributor
New ContributorCyclone 10 LP I/O pins configuration
Hello, I am working with a custom PCB that includes a Cyclone 10 LP FPGA, and I am using Quartus Prime Lite v20.1.1. On this PCB, some of the output pins drive optical fibers. The problem is that, ...
Hi Francisco,
pin options become active after loading configuration bistreams. In unconfigured state, FPGA IO pins are still driven by weak pull-up and can produce unwanted output signals.
There are two ways to overcome the situation:
- Change logic polarity to active-low
- Use strong pull-down resistors (e.g. 0.5 - 1k) to override pull-up.
Regards Frank
