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francisco-padilla-ed's avatar
francisco-padilla-ed
Icon for New Contributor rankNew Contributor
8 days ago
Solved

Cyclone 10 LP I/O pins configuration

Hello, I am working with a custom PCB that includes a Cyclone 10 LP FPGA, and I am using Quartus Prime Lite v20.1.1. On this PCB, some of the output pins drive optical fibers. The problem is that, ...
Configuration
Generic Io
Power
  • FvM's avatar
    FvM
    8 days ago

    Hi Francisco,

    pin options become active after loading configuration bistreams. In unconfigured state, FPGA IO pins are still driven by weak pull-up and can produce unwanted output signals.

    There are two ways to overcome the situation:

    • Change logic polarity to active-low
    • Use strong pull-down resistors (e.g. 0.5 - 1k) to override pull-up.

    Regards Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
8 days ago

Hi Francisco,

pin options become active after loading configuration bistreams. In unconfigured state, FPGA IO pins are still driven by weak pull-up and can produce unwanted output signals.

There are two ways to overcome the situation:

  • Change logic polarity to active-low
  • Use strong pull-down resistors (e.g. 0.5 - 1k) to override pull-up.

Regards Frank

AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
7 days ago

Yes, FvM is correct. You can refer to this configuration sequence where the I/O pins are tied to an internal weak pull-up when the device is powered on.