Counting on falling and rising edge of clock

hi is it possible to design

dual edge counter in altera , what which is possible in xilinx cool runner series

reagards

baba

-- Xilinx ---

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

entity CNT2 is

port( data : in STD_LOGIC_VECTOR (1 downto 0); -- Parallel data in

cnt_en : in STD_LOGIC; -- Count enable

load : in STD_LOGIC; -- Load line enable

clr : in STD_LOGIC; -- Active low clear

clk : in STD_LOGIC; -- Clock

qout : inout STD_LOGIC_VECTOR (1 downto 0));

end CNT2;

architecture rtl of CNT2 is

signal q_int : UNSIGNED (1 downto 0);

begin

process(clk, clr)

begin -- Clear output register

if (clr = '0') then q_int <= (others => '0');-- Counting on falling and rising edge of clock

elsif clk'event then

if (load = '1') then q_int <= UNSIGNED(data);-- Load in start value

elsif cnt_en = '1' then q_int <= q_int + 1;-- If count enable is high

end if;

end if;

end process;

qout <= STD_LOGIC_VECTOR(q_int);

end rtl;

-- Altera i changed it like this --

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_arith.all;

use IEEE.STD_LOGIC_unsigned.all;

entity dual is

port( cnt_en : in STD_LOGIC;

data : in STD_LOGIC_VECTOR (7 downto 0);

load : in STD_LOGIC;

clr : in STD_LOGIC;

clk : in STD_LOGIC;

qout : inout STD_LOGIC_VECTOR (7 downto 0));

end dual;

architecture rtl of dual is

signal q_int_o,q_int_e : UNSIGNED (7 downto 0);

begin

process(clk, clr)

begin

if (clr = '0') then q_int_o <= "00000001";

elsif clk'event and clk='1' then

if (load = '1') then

if data(0) ='1' then q_int_o <= UNSIGNED(data);

else q_int_o <= UNSIGNED(data)+1;

end if;-- Load in start value

elsif cnt_en = '1' then q_int_o <= q_int_o + 2;-- If count enable is high

end if;

end if;

end process;

process(clk, clr)

begin

if (clr = '0') then q_int_e <= (others => '0');

elsif clk'event and clk='0' then

if (load = '1') then

if data(0) ='0' then q_int_e <= UNSIGNED(data);

else q_int_e <= UNSIGNED(data)-1;

end if;

elsif cnt_en = '1' then q_int_e <= q_int_e + 2;end if;

end if;

end process;

qout <= STD_LOGIC_VECTOR(q_int_e) when clk='0' else STD_LOGIC_VECTOR(q_int_o) when clk='1';

end rtl;