Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCounting on falling and rising edge of clock
hi is it possible to design dual edge counter in altera , what which is possible in xilinx cool runner series reagards baba -- Xilinx --- library IEEE; use IEEE.std_logic_11...
Altera_ForumHonored Contributor
Honored ContributorHow is this done in Xilinx? I had someone target this for V5 in ISE, and after cleaning up the errors(entity changes from CNT to CNT2, and RESET_ACTIVE is undefined), it errors out with "unsupported clock statement".
If your device has a PLL, you can create a 2x clock and use that for the counter. If there isn't, you can have a counter that counts on the rising edge, and then add an LSB that is the inversion of the clock(This requires you to understand the timing analysis that occurs, and really depends on what this counter feeds and what you're actually trying to show...)
