Counter1 "q" o/p needs to be fed into the ROM "A_address" input .... Please Help.

Hello ABlackBox.

I think you're trying to connect the output of the counter module ( q ) to the address of the rom_unit. To do this you should use an internal signal vector:

signal int_address : std_logic_vector(WIDTH-1 downto 0) -- I don't know how many bits the address needs. Declare the constant WIDTH or simply

-- replace with a numeric value

BEGIN

rom_unit : variation1

PORT map

(

address => int_address,

clken => '1',

clock => sclk,

q => Data

);

counter_unit : counter1

PORT map

(

clock => clock,

updown => '1',

q => int_address

);

End Behavioural;

I declare int_address between "architecture" and "begin". You have A_address as an input on top level entity. Do you really need it?

Hi Bertulus,

Thanks for you Reply, I will try this code now and let you know, also I don't really need A_address I just used it to make different then the address in the rest of the code

"component Variation1" uses address. but yeah I would give this a go and get back to let you know :) Thanks a mill.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY lpm;

USE lpm.lpm_components.all;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY LPM_ROM_MEGAFUNCTION IS

PORT( A_address :IN std_logic_vector (0 downto 0);

Sclk, clock :IN std_logic;

Data,q :OUT STD_LOGIC_VECTOR (0 DOWNTO 0));

END LPM_ROM_MEGAFUNCTION;

Architecture Behavioural of LPM_ROM_MEGAFUNCTION is

component Variation1

PORT

(

address : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

clken : IN STD_LOGIC := '1';

clock : IN STD_LOGIC := '1';

q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

end component;

component Counter1

PORT

(

clock : IN STD_LOGIC ;

updown : IN STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

end component;

-- std_logic_vector(WIDTH-1 downto 0)

-- I don't know how many bits the address needs. Declare the constant WIDTH or simply

-- replace with a numeric value

Signal int_address : std_logic_vector(0 downto 0);

BEGIN

rom_unit : variation1

PORT map

(

address => int_address,

clken => '1',

clock => sclk,

q => Data

);

counter_unit : counter1

PORT map

(

clock => clock,

updown => '1',

q=> int_address

);

int_address => A_address;

End Behavioural;

============================================================================================================

I have made the changes I have assigned a signal to q from the counter module and then fed that signal into the Rom Module compiler doesn't like it and returns the following:

Info: *******************************************************************

Info: Running Quartus II Analysis & Synthesis

Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition

Info: Processing started: Sun Nov 03 23:56:43 2013

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off LPM_ROM_MEGAFUNCTION -c LPM_ROM_MEGAFUNCTION

Info: Found 2 design units, including 1 entities, in source file variation1.vhd

Info: Found design unit 1: variation1-SYN

Info: Found entity 1: Variation1

Error (10500): VHDL syntax error at LPM_ROM_MEGAFUNCTION.vhd(60) near text "=>"; expecting "(", or "'", or "."

Info: Found 0 design units, including 0 entities, in source file lpm_rom_megafunction.vhd

Info: Found 2 design units, including 1 entities, in source file counter1.vhd

Info: Found design unit 1: counter1-SYN

Info: Found entity 1: Counter1

Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Error: Peak virtual memory: 239 megabytes

Error: Processing ended: Sun Nov 03 23:56:44 2013

Error: Elapsed time: 00:00:01

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

Two things:

a-The error now is in the line:

int_address => A_address;

the assigment operator is <=. The corrected line is:

int_address <= A_address;

b-There will be an error again. The moduler counter_unit generate on its outputs the int_address vector. But you also receive this vector from outside of the top level entity ( A_address is an input to the circuit ). So you have a contention on signal int_address.

May be you should use a multiplexor. In a special condition of the circuit you use the counter output, in other condition you use A_address. But this depends of how your circuit should behave.

I just figured the bus contention and for the time being I got rid of the A_address so I wouldn't require a multiplexor module, if I did require an external way of feeding in

A_address, I would go and implement it with a multiplexor module. Thank you so very much Bertulus, you are a star.