Counter1 "q" o/p needs to be fed into the ROM "A_address" input .... Please Help.

Hello ABlackBox.

I think you're trying to connect the output of the counter module ( q ) to the address of the rom_unit. To do this you should use an internal signal vector:

signal int_address : std_logic_vector(WIDTH-1 downto 0) -- I don't know how many bits the address needs. Declare the constant WIDTH or simply

-- replace with a numeric value

BEGIN

rom_unit : variation1

PORT map

(

address => int_address,

clken => '1',

clock => sclk,

q => Data

);

counter_unit : counter1

PORT map

(

clock => clock,

updown => '1',

q => int_address

);

End Behavioural;

I declare int_address between "architecture" and "begin". You have A_address as an input on top level entity. Do you really need it?