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hello
i do counter to 24 hour and test it with one second ... in modelsim it works fine but in cyclone 2 it count like this 1,2,3,4,5,6,7,8,9 - > 12 19 -> 22 29 -> 33 it jumps with 3 ... i can't undderstant why please helpppp12 Replies
Altera_Forum--- Quote Start --- i use modelsim for rtl and complie all files in the project in rtl simulation i understand normal simulation with model sim --- Quote End --- ps. I install modelsim altera and i read in the document the method for stating gate level simulation:
but is there some easier way for this kind of simulation - something like standart modelsim simulation with forcing of signals ?Compiling Testbench and Design Files into the Work Library The following instructions show you how to compile your testbench and design files into the work library using the ModelSim-Altera GUI. 1. Browse to locate your designs. 2. Click OK. To create the work library, perform the following steps: 1. In the ModelSim-Altera software, on the File menu, point to New and click Library. The Create a New Library dialog box appears.- Altera_Forum
i use modelsim for rtl and complie all files in the project
in rtl simulation i understand normal simulation with model sim - Altera_Forum
Timming analysis is found in Quartus, either the Classical Timming Analyzer or the TimeQuest Timming Analyzer (prefered).
But let me ask this again: When you do RTL level simulation, does your complete design work properly or is it just some components that work OK? - Altera_Forum
the code of the conters is :
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity hours2 is port (CLK2h: in std_logic ; Reset2h: in std_logic; Q2h: out std_logic_vector (1 downto 0); Q1: out std_logic); end hours2; architecture beh of hours2 is signal count2 : std_logic_vector (1 downto 0); begin process (CLK2h, Reset2h) begin if Reset2h ='1' then count2 <= "00"; elsif (CLK2h'event and CLK2h = '0') then count2 <= count2 + 1; end if; end process ; Q2h <= count2 ; Q1 <= count2 (1); end beh ;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity hours10 is port (CLK10h: in std_logic ; Reset10h: in std_logic; Q10h: out std_logic_vector (3 downto 0); Q2: out std_logic; Q3: out std_logic); end hours10; architecture beh of hours10 is signal count : std_logic_vector (3 downto 0); begin process (CLK10h, Reset10h) begin if Reset10h ='1' then count <= "0000"; elsif (CLK10h'event and CLK10h = '0') then if count= "1001" then count <= "0000"; else count <= count + 1; end if; end if; end process ; Q10h <= count ; Q2 <= count (2); Q3 <= count (3); end beh ;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity min10 is port (CLK10min: in std_logic ; Reset10min: in std_logic; Q10min: out std_logic_vector (3 downto 0); Q_10min_signal : out std_logic); end min10; architecture beh of min10 is signal count : std_logic_vector (3 downto 0); begin process (CLK10min, Reset10min) begin if Reset10min ='1' then count <= "0000"; elsif (CLK10min'event and CLK10min = '0') then if count= "1001" then count <= "0000"; else count <= count + 1; end if; end if; end process ; Q10min <= count ; Q_10min_signal <= count (3); end beh ;
if i test the cointer to 60 (counter to 10 min and counter to 6) it works fine ... if i connect the counter to 24 it stat to jump from 9 to 12, from 19 to 22, from 29 to 33library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity min60 is port (CLK60min: in std_logic ; Reset60min: in std_logic; Q60min: out std_logic_vector (3 downto 0); Q_60min_signal : out std_logic); end min60; architecture beh of min60 is signal count : std_logic_vector (3 downto 0); begin process (CLK60min, Reset60min) begin if Reset60min ='1' then count <= "0000"; elsif (CLK60min'event and CLK60min = '0') then if count= "0101" then count <= "0000"; else count <= count + 1; end if; end if; end process ; Q60min <= count ; Q_60min_signal <= count (2); end beh ; - Altera_Forum
the code is :
library ieee; --library ieee is used use ieee.std_logic_1164.all; --the package std_logic_1164 is used use ieee.std_logic_unsigned.all; --the package std_logic_unsigned is used use ieee.std_logic_arith.all; --the package std_logic_arith is used entity hours24 is port (CLK24h: in std_logic ; Reset24h: in std_logic; Q107: out std_logic_vector (6 downto 0); Q27: out std_logic_vector (6 downto 0)); end hours24; architecture structure of hours24 is component hours10 is port (CLK10h: in std_logic ; Reset10h: in std_logic; Q10h: out std_logic_vector (3 downto 0); Q2: out std_logic; Q3: out std_logic); end component ; component hours2 is port (CLK2h: in std_logic ; Reset2h: in std_logic; Q2h: out std_logic_vector (1 downto 0); Q1: out std_logic); end component ; component AND_ent is port( x: in std_logic; y: in std_logic; F: out std_logic); end component ; component min10 is port (CLK10min: in std_logic ; Reset10min: in std_logic; Q10min: out std_logic_vector (3 downto 0); Q_10min_signal : out std_logic); end component ; component min60 is port (CLK60min: in std_logic ; Reset60min: in std_logic; Q60min: out std_logic_vector (3 downto 0); Q_60min_signal : out std_logic); end component ; component OR_ent is port( x1: in std_logic; y1: in std_logic; F1: out std_logic ); end component ; component freqdiv is --entity freqdiv is proposed port (CLKfr: in std_logic ; --CLKfr signal of freqdiv Resetfr: in std_logic; --Resetfr signal of freqdiv Q: out std_logic); end component ; component encoder10 is --entity dispencoder is proposed port(I0: in std_logic_vector (3 downto 0); --I signal Oenc0: out std_logic_vector (6 downto 0)); end component ; component encoder2 is --entity dispencoder is proposed port(I1: in std_logic_vector (1 downto 0); --I signal Oenc1: out std_logic_vector (6 downto 0)); --Oenc output signal end component ; signal CAND1, CAND2, RST24, RST24h, Q3CLK, FRQ : std_logic ; signal ENC10 : std_logic_vector (3 downto 0); signal ENC2 : std_logic_vector (1 downto 0); signal ten_min : std_logic ; signal ten_min_vect : std_logic_vector (3 downto 0); signal sixty_min_vect : std_logic_vector (3 downto 0); signal sixty_min_int_signal : std_logic ; begin min10Inst : min10 port map (FRQ, Reset24h,ten_min_vect, ten_min); min60Inst : min60 port map (ten_min, Reset24h,sixty_min_vect, sixty_min_int_signal); h10: hours10 port map (sixty_min_int_signal, RST24h, ENC10, CAND1, Q3CLK); h2: hours2 port map (Q3CLK, RST24h, ENC2, CAND2); a1: AND_ent port map (CAND1, CAND2, RST24 ); o2: OR_ent port map (Reset24h, RST24, RST24h ); fd: freqdiv port map (CLK24h, Reset24h, FRQ); e10: encoder10 port map (ENC10, Q107); e2: encoder2 port map (ENC2, Q27); end structure; - Altera_Forum
where can i find tis timing analis - in model sim or in quartus ?
is this gate-level timing simulation - Altera_Forum
Gate Level Simulation in ModelSim starts on page 11:
http://www.altera.com/literature/hb/qts/qts_qii53001.pdf though i would recommend using timing analysis as mentioned above. - Altera_Forum
hmm i use simulate -> start simulation in model sim
where can i find the gate level simulation in modelsim - Altera_Forum
Well, if you used ModelSim for RTL, I'd use it for gate level as well.
What you should look for is to see if your design still behaves correctly in gate level simulation or not. - Altera_Forum
i found in quartus such timing simulation ... what i should look in the report ?
