counter

the code of the conters is :

library    ieee;                                  
use ieee.std_logic_1164.all;                    
use ieee.std_logic_unsigned.all;               
use ieee.std_logic_arith.all;                  
entity hours2 is                              
  port (CLK2h: in std_logic ;                  
  Reset2h: in std_logic;                         
  Q2h: out std_logic_vector (1 downto 0);                           
  Q1: out std_logic);                           
end hours2;                                   
architecture beh of hours2 is                 
signal count2 : std_logic_vector (1 downto 0); 
begin                                          
  process (CLK2h, Reset2h)                     
     begin                                     
     if Reset2h ='1'                           
    then count2 <= "00";
     
    elsif (CLK2h'event and CLK2h = '0')         
   then  count2 <= count2 + 1;                   
                                 
  end if;                                      
  end process ;                                
  
    Q2h <= count2 ;                        
    Q1 <= count2  (1); 
                      
    end beh ;                                  
    

library    ieee;                                  
use ieee.std_logic_1164.all;                    
use ieee.std_logic_unsigned.all;               
use ieee.std_logic_arith.all;                  
entity hours10 is                              
  port (CLK10h: in std_logic ;                  
  Reset10h: in std_logic;          
  Q10h: out std_logic_vector (3 downto 0);                           
  Q2: out std_logic; 
  Q3: out std_logic);                          
end hours10;                                   
architecture beh of hours10 is                 
signal count : std_logic_vector (3 downto 0); 
begin                                          
  process (CLK10h, Reset10h)                     
     begin                                     
     if Reset10h ='1'                           
    then count <= "0000";
     
    elsif (CLK10h'event and CLK10h = '0')         
   then                     
  if  count= "1001" then 
  count <= "0000";  else count <= count + 1;     
                 
  end if;                                         
  end if;                                      
  end process ;                                
  
    Q10h <= count ;                        
    Q2 <= count  (2);  
    Q3  <= count  (3);
                     
    end beh ;             

library    ieee;                                  
use ieee.std_logic_1164.all;                    
use ieee.std_logic_unsigned.all;               
use ieee.std_logic_arith.all;                  
entity min10 is                              
  port (CLK10min: in std_logic ;                  
  Reset10min: in std_logic;          
  Q10min: out std_logic_vector (3 downto 0);                           
  Q_10min_signal : out std_logic);                          
end min10;                                   
architecture beh of min10 is                 
signal count : std_logic_vector (3 downto 0); 
begin                                          
  process (CLK10min, Reset10min)                     
     begin                                     
     if Reset10min ='1'                           
    then count <= "0000";
     
    elsif (CLK10min'event and CLK10min = '0')         
   then                     
  if  count= "1001" then 
  count <= "0000";  else count <= count + 1;     
                 
  end if;                                         
  end if;                                      
  end process ;                                
  
    Q10min <= count ;                        
  
    Q_10min_signal  <= count  (3);
                     
    end beh ;                                  
  

library    ieee;                                  
use ieee.std_logic_1164.all;                    
use ieee.std_logic_unsigned.all;               
use ieee.std_logic_arith.all;                  
entity min60 is                              
  port (CLK60min: in std_logic ;                  
  Reset60min: in std_logic;          
  Q60min: out std_logic_vector (3 downto 0);                           
  Q_60min_signal : out std_logic);                          
end min60;                                   
architecture beh of min60 is                 
signal count : std_logic_vector (3 downto 0); 
begin                                          
  process (CLK60min, Reset60min)                     
     begin                                     
     if Reset60min ='1'                           
    then count <= "0000";
     
    elsif (CLK60min'event and CLK60min = '0')         
   then                     
  if  count= "0101" then 
  count <= "0000";  else count <= count + 1;     
                 
  end if;                                         
  end if;                                      
  end process ;                                
  
    Q60min <= count ;                        
  
    Q_60min_signal  <= count (2);
                     
    end beh ;