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the code is :

library    ieee;                                          --library ieee is used
use ieee.std_logic_1164.all;                           --the package std_logic_1164 is used 
use ieee.std_logic_unsigned.all;                       --the package std_logic_unsigned is used
use ieee.std_logic_arith.all;                          --the package std_logic_arith is used    
entity hours24 is                                    
  port (CLK24h: in std_logic ;                        
  Reset24h: in std_logic;                             
  Q107: out std_logic_vector (6 downto 0);            
  Q27: out std_logic_vector (6 downto 0));           
end hours24;                                        
architecture  structure of hours24 is                
component hours10 is
port (CLK10h: in std_logic ;                  
Reset10h: in std_logic;                       
Q10h: out std_logic_vector (3 downto 0);                           
Q2: out std_logic;
Q3: out std_logic);  
end component ;                                         
component hours2 is                              
port (CLK2h: in std_logic ;                  
Reset2h: in std_logic;                       
Q2h: out std_logic_vector (1 downto 0);                           
Q1: out std_logic);
end component ;                                
                
component AND_ent is
port(    x: in std_logic;
y: in std_logic;
F: out std_logic);
end component ;  
component min10 is                              
  port (CLK10min: in std_logic ;                  
  Reset10min: in std_logic;          
  Q10min: out std_logic_vector (3 downto 0);                           
  Q_10min_signal : out std_logic);                          
 end component  ; 
  
  component min60 is                              
  port (CLK60min: in std_logic ;                  
  Reset60min: in std_logic;          
  Q60min: out std_logic_vector (3 downto 0);                           
  Q_60min_signal : out std_logic);                          
end component ;   
                             
component  OR_ent is
port(    x1: in std_logic;
y1: in std_logic;
F1: out std_logic );                
end component ; 
component freqdiv is                              --entity freqdiv is proposed
  port (CLKfr: in std_logic ;                  --CLKfr signal of freqdiv 
  Resetfr: in std_logic;                       --Resetfr signal of freqdiv
  Q: out std_logic);  
end component ;
 
component encoder10 is                                --entity dispencoder is proposed
port(I0: in std_logic_vector (3 downto 0);           --I signal 
  Oenc0: out std_logic_vector (6 downto 0));
 end component ;
component encoder2 is                                --entity dispencoder is proposed
port(I1: in std_logic_vector (1 downto 0);           --I signal 
  Oenc1: out std_logic_vector (6 downto 0));         --Oenc output signal
end component ;
      
signal CAND1, CAND2, RST24, RST24h, Q3CLK, FRQ : std_logic ;                          
signal ENC10 : std_logic_vector (3 downto 0);
signal ENC2 : std_logic_vector (1 downto 0);
signal ten_min : std_logic ;         
signal ten_min_vect : std_logic_vector (3 downto 0);   
signal sixty_min_vect : std_logic_vector (3 downto 0);   
signal sixty_min_int_signal : std_logic ;  
                        
                                
                        
begin
min10Inst : min10 port map (FRQ, Reset24h,ten_min_vect, ten_min); 
min60Inst : min60 port map (ten_min, Reset24h,sixty_min_vect, sixty_min_int_signal); 
h10: hours10 port map (sixty_min_int_signal, RST24h, ENC10, CAND1, Q3CLK);   
h2: hours2 port map (Q3CLK, RST24h, ENC2, CAND2);   
a1: AND_ent port map (CAND1, CAND2, RST24 );
o2: OR_ent port map (Reset24h, RST24, RST24h );
fd: freqdiv port map (CLK24h, Reset24h, FRQ);
e10: encoder10 port map (ENC10, Q107); 
e2: encoder2 port map (ENC2, Q27);
                  
end structure;