Could some one explain some thing in this schematic please :)

Thanks for your tips i shall follow all of them :)

"Create an HDL design of all the pins you plan on using before you finalize the design"

i always do this one hehe :)

once i have checked over my design is it ok if i upload the schematic for you to have a quick once over? it is very simple.

Thank you :)

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once i have checked over my design is it ok if i upload the schematic for you to have a quick once over? it is very simple.

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Yep, no problem.

When you draw your schematic, use text to add notes, eg., add a list of reference documents like the handbook and pin connections guidelines, and notes that you have followed their recommendations. This helps a reviewer quickly understand that you have reviewed the FPGA literature.

Here's an example to give you ideas:

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf

Cheers,

Dave

had a quick look at pinout and did not see any special power pins

here is my schematic :)

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had a quick look at pinout and did not see any special power pins

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There are no notes showing your design process/analysis, so how can someone review your design. Showing a schematic is as bad as just asking, "Hey, can you reverse engineer this design for me". Please show that you have put some thought into the schematic design.

For example,

1) The FT2232D EEPROM signals are 5V logic levels - read the data sheet (they are powered by VCC on the device, not VCCIO). The 93LC46B EEPROM powered at 3.3V has a VIH(max) of VCC+1V = 4.3V. So you have violated the input voltage of the EEPROM.

2) What are the voltages expected on the dot matrix display header? How are you going to protect your FPGA against 5V devices? At least put a note next to the header on the schematic to remind yourself its only 3.3V tolerant. (Its possible the Cyclone 1 is 5V tolerant - I did not look at the handbook - that is your job - put a note on the schematic).

3) What are the voltages expected on the SPI header. Same comments as (2).

4) Put source terminations on anything that is a clock, eg., the DCLK output from the FTDI chip, the SCLK to the SPI connector, and the clock oscillator.

5) You probably want to add a filter to the PLL voltage pin, eg., a pi filter constructed from two capacitors and a ferrite bead (see the schematic I linked to).

6) I don't like zapping FPGA pins by touching header pins on boards, so I either put a buffer between a header and the FPGA, or a 100-ohm series resistance. I'd recommend you at least put some resistance on the board. You can always change them to zero ohm jumpers if needed.

7) Decouple every power pin on the FPGA. I don't think you have enough VCCIO (3.3V) decoupling caps.

8) Add a decoupling cap to your oscillator VCC pin. Put the cap next to the oscillator to indicate that is where it should go on the PCB layout. Actually, put the decoupling next to the device it is supposed to decouple for all your components.

9) Change the pin assignment for INIT_DONE to drive the LED signal. You can then use it as INIT_DONE, the LED will come on when the device is configured, or as a general purpose LED.

10) Explain your configuration scheme. I see the EPCS EEPROM, but I also see the connection to the FTDI. What is the scheme you plan on using to configure the device? MSEL = 00b selects what? (I didn't look at the data sheet, and I should not have to, you should have a note indicating you are selecting the configuration scheme, eg., AS, PS, etc)

11) Why are you routing nCE and nCEO to the FTDI pins? They're not really any use to you. nCE should be tied to ground, and CONF_DONE and INIT_DONE are the pins you want to see if you are using passive serial configuration from the FTDI. If you are planning on using both PS and AS modes, then I suspect you will need to control the MSEL pins.

12) Look at the FTDI Morphic-II schematic. What do they do for their programming interface?

This feedback is intended to be constructive. I did give you a link and ask you to take note of the schematic style. Now I hope you understand why. A review is to confirm your design process as well as the end product (the schematic, board layout, HDL files, etc etc).

The above will keep you busy, and will help you improve your design presentation skills.

Cheers,

Dave

wow thats a detailed response thanks for that it IS very helpful.

i intend to configure the device using this process. (so AS + my JTAG)

http://lalusb.free.fr/fwloader.html#introduction

and they have nCE,nCEO connected to the FTDI device (are you saying these pins are not needed?). I want to configure this device using just JTAG for quick testing and the FTDI will program it using its B port as well. (also configuring the EPCS4)

The dot matrix header is an output only, but some resistors for zap protection would not hurt!!! :)

i have only included decoupling caps for the FPGA io banks i am using, should i include them for io banks that i do not use?

ill make sure i select a suitable eeprom device as well :)

i have read all your comments they are VERY useful and ill try and amend my design to correct all of them :) Thanks for taking the time to check it over and help me improve my design :)

had a quick read of the FT2232 datasheet and they suggest the 93LC46B thats the reason i picked it.

"There are two varieties of 93C46/56/66 EEPROM‟s on the market – one is configured as being 16 bits wide, the other is configured as being 8 bits wide. These are available from many sources such as Microchip, STMicro, ISSI etc. The"

just checked the datasheet

http://uk.rs-online.com/web/p/eeprom/0454246/

it can be run at 5v unless i have miss read it?

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had a quick read of the FT2232 datasheet and they suggest the 93LC46B thats the reason i picked it.

"There are two varieties of 93C46/56/66 EEPROM‟s on the market – one is configured as being 16 bits wide, the other is configured as being 8 bits wide. These are available from many sources such as Microchip, STMicro, ISSI etc. The"

just checked the datasheet

http://uk.rs-online.com/web/p/eeprom/0454246/

it can be run at 5v unless i have miss read it?

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That is correct, but you should be powering the 93LC46B at 5V, not 3.3V. Look at your schematic, both VCC and the pullup are currently to 3.3V.

Cheers,

Dave

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i intend to configure the device using this process. (so AS + my JTAG)

http://lalusb.free.fr/fwloader.html#introduction

and they have nCE,nCEO connected to the FTDI device (are you saying these pins are not needed?). I want to configure this device using just JTAG for quick testing and the FTDI will program it using its B port as well. (also configuring the EPCS4)

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There are three devices on the EPCS serial interface; the FTDI, the EPCS, and the FPGA. What is to stop pin conflicts? Describe the possible use-cases, eg., when you use the FTDI to program the device, how does it become the 'bus master'?

This is the kind of detail you put into a design document. It helps you remember why you did stuff, and it allows you to more completely understand the design. Just because someone else did it, and it works, does not mean it is error free. You need to review this scheme and understand whether or not there is a case where you can create a driver conflict.

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i have only included decoupling caps for the FPGA io banks i am using, should i include them for io banks that i do not use?

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Yes. Always start with a complete design. When you are laying out the PCB, if you have to make trade-offs, then you can start deleting decoupling. Start with good habits.

Cheers,

Dave

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I want to configure this device using just JTAG for quick testing

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Why not use MPSSE mode for JTAG programming directly?

You could wire the FTDI to the JTAG chain and then program either the FPGA or the EPCS device.

You could add a multiplexer, or tri-state the FTDI pins, and still be able to use the external JTAG connector.

Cheers,

Dave

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That is correct, but you should be powering the 93LC46B at 5V, not 3.3V. Look at your schematic, both VCC and the pullup are currently to 3.3V.

Cheers,

Dave

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sorry i completely see your point now :)

thanks :)

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Why not use MPSSE mode for JTAG programming directly?

You could wire the FTDI to the JTAG chain and then program either the FPGA or the EPCS device.

You could add a multiplexer, or tri-state the FTDI pins, and still be able to use the external JTAG connector.

Cheers,

Dave

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dont really want to go down the multiplier / tri state route as i want to keep this design cheap and as simple as it can be

the JTAG header doesn't really need to be there at all. its just for the first prototype pcb really just for backup - when in production i wont even solder a header onto it!

i have heard of this MPSSE mode and i know the FTDI can do it. but i did a bit of research on it and could not find much info on software that does the actual programming side of it. so decided to go with the other method instead which i KNOW works as i have tested it on a demo rig i have built using this FPGA and the FTDI chip :) it comes with a really nice c library i can wrap up in a nice little firmware upgrade tool i can give to people who want to update the firmware on this device in the future :)