Could some one explain some thing in this schematic please :)

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i intend to configure the device using this process. (so AS + my JTAG)

http://lalusb.free.fr/fwloader.html#introduction

and they have nCE,nCEO connected to the FTDI device (are you saying these pins are not needed?). I want to configure this device using just JTAG for quick testing and the FTDI will program it using its B port as well. (also configuring the EPCS4)

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There are three devices on the EPCS serial interface; the FTDI, the EPCS, and the FPGA. What is to stop pin conflicts? Describe the possible use-cases, eg., when you use the FTDI to program the device, how does it become the 'bus master'?

This is the kind of detail you put into a design document. It helps you remember why you did stuff, and it allows you to more completely understand the design. Just because someone else did it, and it works, does not mean it is error free. You need to review this scheme and understand whether or not there is a case where you can create a driver conflict.

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i have only included decoupling caps for the FPGA io banks i am using, should i include them for io banks that i do not use?

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Yes. Always start with a complete design. When you are laying out the PCB, if you have to make trade-offs, then you can start deleting decoupling. Start with good habits.

Cheers,

Dave