--- Quote Start ---
had a quick look at pinout and did not see any special power pins
--- Quote End ---
There are no notes showing your
design process/analysis, so how can someone
review your design. Showing a schematic is as bad as just asking, "Hey, can you reverse engineer this design for me". Please show that you have put some thought into the schematic design.
For example,
1) The FT2232D EEPROM signals are 5V logic levels - read the data sheet (they are powered by VCC on the device, not VCCIO). The 93LC46B EEPROM powered at 3.3V has a VIH(max) of VCC+1V = 4.3V. So you have violated the input voltage of the EEPROM.
2) What are the voltages expected on the dot matrix display header? How are you going to protect your FPGA against 5V devices? At least put a note next to the header on the schematic to remind yourself its only 3.3V tolerant. (Its possible the Cyclone 1 is 5V tolerant - I did not look at the handbook - that is your job - put a note on the schematic).
3) What are the voltages expected on the SPI header. Same comments as (2).
4) Put source terminations on anything that is a clock, eg., the DCLK output from the FTDI chip, the SCLK to the SPI connector, and the clock oscillator.
5) You probably want to add a filter to the PLL voltage pin, eg., a pi filter constructed from two capacitors and a ferrite bead (see the schematic I linked to).
6) I don't like zapping FPGA pins by touching header pins on boards, so I either put a buffer between a header and the FPGA, or a 100-ohm series resistance. I'd recommend you at least put some resistance on the board. You can always change them to zero ohm jumpers if needed.
7) Decouple every power pin on the FPGA. I don't think you have enough VCCIO (3.3V) decoupling caps.
8) Add a decoupling cap to your oscillator VCC pin. Put the cap next to the oscillator to indicate that is where it should go on the PCB layout. Actually, put the decoupling next to the device it is supposed to decouple for all your components.
9) Change the pin assignment for INIT_DONE to drive the LED signal. You can then use it as INIT_DONE, the LED will come on when the device is configured, or as a general purpose LED.
10) Explain your configuration scheme. I see the EPCS EEPROM, but I also see the connection to the FTDI. What is the scheme you plan on using to configure the device? MSEL = 00b selects what? (I didn't look at the data sheet, and I should not have to, you should have a note indicating you are selecting the configuration scheme, eg., AS, PS, etc)
11) Why are you routing nCE and nCEO to the FTDI pins? They're not really any use to you. nCE should be tied to ground, and CONF_DONE and INIT_DONE are the pins you want to see if you are using passive serial configuration from the FTDI. If you are planning on using both PS and AS modes, then I suspect you will need to control the MSEL pins.
12) Look at the FTDI Morphic-II schematic. What do they do for their programming interface?
This feedback is intended to be constructive. I did give you a link and ask you to take note of the schematic style. Now I hope you understand why. A
review is to confirm your
design process as well as the end product (the schematic, board layout, HDL files, etc etc).
The above will keep you busy, and will help you improve your design presentation skills.
Cheers,
Dave
Honored Contributor
