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Altera_Forum's avatar
Altera_Forum
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14 years ago

Could some one explain some thing in this schematic please :)

Im very new to FPGA's and am using this attached schematic to crib from. every thing makes sense apart from the following FPGA pins pins 26,81 held high to 1.2v pins 27,80 held to ground ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

wow thats a detailed response thanks for that it IS very helpful.

i intend to configure the device using this process. (so AS + my JTAG)

http://lalusb.free.fr/fwloader.html#introduction

and they have nCE,nCEO connected to the FTDI device (are you saying these pins are not needed?). I want to configure this device using just JTAG for quick testing and the FTDI will program it using its B port as well. (also configuring the EPCS4)

The dot matrix header is an output only, but some resistors for zap protection would not hurt!!! :)

i have only included decoupling caps for the FPGA io banks i am using, should i include them for io banks that i do not use?

ill make sure i select a suitable eeprom device as well :)

i have read all your comments they are VERY useful and ill try and amend my design to correct all of them :) Thanks for taking the time to check it over and help me improve my design :)