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Altera_Forum
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14 years ago

Configuring clock domains with sdc files

Hello,

For the past few days I have been trying to configure two different clock domains within my top level VHDL entity with no success.

I have one base clock that I'm using to generate a derived clock, and when I try to set false paths between them (or when I try to set them as two exclusive clock groups) the Quartus II Fitter simply ignores these commands.

The sdc file goes like this: 


#  Base clock
create_clock -name {clock_50_MHZ} -period 20.000 -waveform { 0.000 10.000 } 
#  Derived clocks
derive_pll_clocks
create_generated_clock -name {clock_RTL} -divide_by 10 -source |clk}] 
#  Try to set two clock groups, but the Fitter complains saying it is an empty collection
set_clock_groups -exclusive -group  -group 
#  I have also tried to set false paths, but this command is simply ignored
set_false_path -from  -to

Could someone provide me an advice on how to create two clock domains when a slower clock is derived from a base clock?

Thanks,

Thomas.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You're create_generated_clock looks suspicious. I've never applied it to a net. If it's a register, apply it to the register. Also, I believe your source should work, but most users have the upstream source node as the source:

    create_generated_clcok -name clock_RTL -divide_by 10 -source [get_ports clock_50_MHZ] [get_keepers {ada|readdata[0]}]

    Also note that the register needs to be driven by clock_RTL. If it's a ripple clock feeding another ripple clock, then each stage needs to have a generated clock since clocks don't propogate through registers.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Rysc,

    Thanks for you answer. As you pointed out I'm using the "get_nets" command to generate the derived clock. I'm doing that because some VHDL entities' port names in my project can't be found by the "get_pins", "get_ports", "get_keepers" and "get_registers" commands. Actually I find it very confusing...

    For instance, through the RTL viewer I'm able to find a pin named "|rtool_hardware|RTL_ADAPTER_v6:ada|rtl_clk", but when I run the command "get_pins |rtool_hardware|RTL_ADAPTER_v6:ada|rtl_clk" it finds nothing! Do you have any tips on how to get this pin?

    What I'm trying to achieve is to compile two hardware entities with two different timing specifications. Because the communication between these two entities is asynchronous I don't want the Fitter trying to optimize paths between them.

    I think my main problem is not knowing how to correctly specify CLOCKS and PATHS using Tcl commands.

    Thnaks,

    Thomas.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The RTL viewer just shows what's in your code before optimization. The Technology Map Viewer is a better representation of what's real on the back-end and what you're timing against. That being said, you generally don't need get_nets at all, and get_pins can usually be avoided. I think you're going down the wrong path with those.

    Can you describe how this second clock is created? Is it just a register clocked by clock_50_MHz whose output is used to drive the clock port of other registers? If so, try what I suggested and let us know the results.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hello again Rysc,

    Today I had some time to work in my project and finally I was able to define two clock domains and compile it successfully.

    It was just a matter of specifying the right pin names. The derived clock I was trying to constrain could only be found through it's technology map viewer name, and not by it's rtl viewer name. Thanks for that Rysc!

    Bellow is the final Tcl script for those who are interested, although it is pretty much the same thing described in some Altera white papers: 

    
#  Base clock
create_clock -name {clock_50_MHZ} -period 20.000 -waveform { 0.000 10.000 } 
#  Clocks derived from base clock
derive_pll_clocks
create_generated_clock -name {clock_RTL} -divide_by 5 -source  
#  Specify clock groups to automatically assign false paths
set_clock_groups -exclusive -group  -group

    Thomas.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ahhh, it's a combinatorial node, which is why get_keeper wouldn't work. Good job.