Configuring clock domains with sdc files

Hi Rysc,

Thanks for you answer. As you pointed out I'm using the "get_nets" command to generate the derived clock. I'm doing that because some VHDL entities' port names in my project can't be found by the "get_pins", "get_ports", "get_keepers" and "get_registers" commands. Actually I find it very confusing...

For instance, through the RTL viewer I'm able to find a pin named "|rtool_hardware|RTL_ADAPTER_v6:ada|rtl_clk", but when I run the command "get_pins |rtool_hardware|RTL_ADAPTER_v6:ada|rtl_clk" it finds nothing! Do you have any tips on how to get this pin?

What I'm trying to achieve is to compile two hardware entities with two different timing specifications. Because the communication between these two entities is asynchronous I don't want the Fitter trying to optimize paths between them.

I think my main problem is not knowing how to correctly specify CLOCKS and PATHS using Tcl commands.

Thnaks,

Thomas.