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Altera_Forum
Honored Contributor
14 years agoConfiguring clock domains with sdc files
Hello, For the past few days I have been trying to configure two different clock domains within my top level VHDL entity with no success. I have one base clock that I'm using to generate a...
Altera_Forum
Honored Contributor
14 years agoYou're create_generated_clock looks suspicious. I've never applied it to a net. If it's a register, apply it to the register. Also, I believe your source should work, but most users have the upstream source node as the source:
create_generated_clcok -name clock_RTL -divide_by 10 -source [get_ports clock_50_MHZ] [get_keepers {ada|readdata[0]}] Also note that the register needs to be driven by clock_RTL. If it's a ripple clock feeding another ripple clock, then each stage needs to have a generated clock since clocks don't propogate through registers.