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Altera_Forum
Honored Contributor
Honored ContributorConfiguring clock domains with sdc files
Hello, For the past few days I have been trying to configure two different clock domains within my top level VHDL entity with no success. I have one base clock that I'm using to generate a...
Altera_ForumHonored Contributor
Honored ContributorAhhh, it's a combinatorial node, which is why get_keeper wouldn't work. Good job.
