Configuring clock domains with sdc files

Hello again Rysc,

Today I had some time to work in my project and finally I was able to define two clock domains and compile it successfully.

It was just a matter of specifying the right pin names. The derived clock I was trying to constrain could only be found through it's technology map viewer name, and not by it's rtl viewer name. Thanks for that Rysc!

Bellow is the final Tcl script for those who are interested, although it is pretty much the same thing described in some Altera white papers:

#  Base clock
create_clock -name {clock_50_MHZ} -period 20.000 -waveform { 0.000 10.000 } 
#  Clocks derived from base clock
derive_pll_clocks
create_generated_clock -name {clock_RTL} -divide_by 5 -source  
#  Specify clock groups to automatically assign false paths
set_clock_groups -exclusive -group  -group 

Thomas.