Configuring clock domains with sdc files

The RTL viewer just shows what's in your code before optimization. The Technology Map Viewer is a better representation of what's real on the back-end and what you're timing against. That being said, you generally don't need get_nets at all, and get_pins can usually be avoided. I think you're going down the wrong path with those.

Can you describe how this second clock is created? Is it just a register clocked by clock_50_MHz whose output is used to drive the clock port of other registers? If so, try what I suggested and let us know the results.