mappy5
New Contributor
5 years agoclock signal used as data
I got an error when compiling the RTL provided by the 3rd IP vendor.
Verilog HDL or VHDL error at [~rtlfile name~](line) : unsupported use of clock signal 'clk' , clock used as data
Pointed out for the following code
always @(posedge clk )begin
if( clk == 1'b1) begin <---Error line
~~~~
Is the only way to avoid the error is to fix the RTL?