New ContributorI got an error when compiling the RTL provided by the 3rd IP vendor.
Verilog HDL or VHDL error at [~rtlfile name~](line) : unsupported use of clock signal 'clk' , clock used as data
Pointed out for the following code
always @(posedge clk )begin
if( clk == 1'b1) begin <---Error line
~~~~
Is the only way to avoid the error is to fix the RTL?
Super ContributorIf this is IP from a 3rd party (especially if you purchased it), you should point out the error to them. Yes, that code should be edited. posedge already implies that the clock is high. That if check is unnecessary.
ContributorHi,
Could you kindly share the non confidential design file and steps on how to reproduce the error so that I can duplicate the error from my end and come up with possible fix.
Regards,
Pavee
New ContributorHi,
I understand that the RTL needs to be fixed.
I don't think it is necessary to share the RTL because I know how to fix it.
I wanted to hear if there was a workaround in the Quartus assign option , but I understand that it doesn't , so I'll close it.
Frequent ContributorHi,
Yes, you're correct. There's no Quartus assignment for RTL fix. Since you have the solution to fix the error , I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Thank you.
Regards,
Pavee
