Forum Discussion
mappy5
New Contributor
New Contributorclock signal used as data
I got an error when compiling the RTL provided by the 3rd IP vendor.
Verilog HDL or VHDL error at [~rtlfile name~](line) : unsupported use of clock signal 'clk' , clock used as data
Pointed out...
If this is IP from a 3rd party (especially if you purchased it), you should point out the error to them. Yes, that code should be edited. posedge already implies that the clock is high. That if check is unnecessary.
IntelSupport
Contributor
ContributorHi,
Could you kindly share the non confidential design file and steps on how to reproduce the error so that I can duplicate the error from my end and come up with possible fix.
Regards,
Pavee
