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mappy5's avatar
mappy5
Icon for New Contributor rankNew Contributor
4 years ago
Solved

clock signal used as data

I got an error when compiling the RTL provided by the 3rd IP vendor. Verilog HDL or VHDL error at [~rtlfile name~](line) : unsupported use of clock signal 'clk' , clock used as data Pointed out...
  • sstrell's avatar
    sstrell
    4 years ago

    If this is IP from a 3rd party (especially if you purchased it), you should point out the error to them. Yes, that code should be edited. posedge already implies that the clock is high. That if check is unnecessary.

paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi,


Yes, you're correct. There's no Quartus assignment for RTL fix. Since you have the solution to fix the error , I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Thank you.


Regards,

Pavee