Forum Discussion
mappy5
New Contributor
New Contributorclock signal used as data
I got an error when compiling the RTL provided by the 3rd IP vendor.
Verilog HDL or VHDL error at [~rtlfile name~](line) : unsupported use of clock signal 'clk' , clock used as data
Pointed out...
If this is IP from a 3rd party (especially if you purchased it), you should point out the error to them. Yes, that code should be edited. posedge already implies that the clock is high. That if check is unnecessary.
mappy5New Contributor
New ContributorHi,
I understand that the RTL needs to be fixed.
I don't think it is necessary to share the RTL because I know how to fix it.
I wanted to hear if there was a workaround in the Quartus assign option , but I understand that it doesn't , so I'll close it.
